Ring counters, again!

The use of a ganged flipflop (all clocked together) basically solves the race and (if there's a Schmitt trigger clock) glitching problem. The CD4022, however, is a ripple counter (not synchronous) so will work, but have relatively sloppy timing.

resulting race and glitching that started us down this rabbit hole.

m.

Not sure how you think multiple outputs can change simultaneously without p roducing glitches in a DAC circuit. The problem can be reduced to a desire d accuracy by various means, but it can not be solved systematically.

If you have multiple outputs changing at once, a DAC will always have glitc hing problems. The only issue is whether the glitches can be reduced enoug h to be acceptable.

If this were being done on a single die it would be feasible to use the out put of the decoder to enable 1 of N analog switches connecting the output t o the elements of a resistor ladder designed to produce a sine wave. But t hat is far too much logic for this simple effort using discrete devices.

In the example case here, the slewing of multiple CMOS outputs is the analog output (summed with a resistor network). So as long as the slew is similar in all sections, the output value will evolve linearly in time, making a smooth transition from one state to the next. I'd regard the section-to-section variations on a chip as a very minor concern.

A clock glitch, however, could be more dramatic, up to and including metastable oscillations.

litching problems. The only issue is whether the glitches can be reduced e nough to be acceptable.

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I'm not sure where you are getting your info. First, the CD4022 does not c ontain a ripple counter. It contains a Johnson ring counter. The outputs are decoded, glitch free, using two input AND gates which detect the edge o f the state bit values.

Page 6 shows the schematic.

Then this same data sheet shows the propagation delays from clock to output to be much longer than the transition times, 2:1 for the rising edge and 4 :1 for the falling edge. So it is entirely possible for the variation of p ropagation time to be very significant compared to the slew rate of the out puts.

Using the CD4022 for a sine wave generator provides no significant advantag es over a shift register other than not needing the inverter. It does requ ire twice as many resistors and connections and may have glitches at the tr ansitions due to two signals changing at the same time. The glitching issu e may not be an issue at 200 kHz, but at faster rates the glitches will be more prominent. It's not just a matter of section to section variation, bu t rising edge vs. falling edge effects.

So, the CD4022 has potential problems vs. no advantages.

There's variations; the CD4022 datasheet from RCA had gating delays AFTER the flip-flops, the outputs wouldn't be synchronous even though the flip-flops were buffered.

The NatSemi datasheet does indeed show a better solution, timing-wise. It also omits the Schmitt-trigger clock buffer, which makes setup/hold glitching somewhat more likely.

I found an RCA data sheet and the logic is identical. They ALL have delays after the FFs because the outputs are DECODED. But I don't know what you thought you saw in the RCA data sheet, they are all the same logic.

Reviewing it, you're right; two minor differences (Schmitt trigger in RCA, and three-input gate in the National Semiconductor) but the Q-to-output pin delays should all match, in both cases.

Still prefer the flipflop solution without decoder, because flipflop clock-to-output delay is as regular as timing gets (independent of clock slew rate, for instance).

es not contain a ripple counter. It contains a Johnson ring counter. The outputs are decoded, glitch free, using two input AND gates which detect th e edge of the state bit values.

FTER the

lays after the FFs because the outputs are DECODED. But I don't know what you thought you saw in the RCA data sheet, they are all the same logic.

, and three-input

k-to-output delay is

That's why the Johnson ring counter is a good solution. No decoding requir ed and only one output changes on each clock, so the inevitable asymmetries don't cause glitches.