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Review this Goofy 555 Based SMPS Design

I've seen source resistors used many times for MOS overcurrent protection. I did think about doing the same for loop control. So...If I understand your idea:

1) Switch is on 2) Switch off at peak switch current or peak of integrator 3) Stall until integrator valley point reached 4) Go to 1

It'll probably work. I'll think about it. Do you know if source resistors increase EMI? When the switch turns on the Cuk network gets lifted fast by the Vdrop on the source resistor.

Aside from that....Maybe I could monitor both the mos and catch diode currents....I'll look into that after I get some sleep..

Thanks for the thought.

D from BC

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D from BC
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Ermmmmmm.... Not quite.

Notice 'average switch current is the input current'. The switch current during switch on time is input current + output current. The switch current during switch off time is.... zero. However the switch on time is controlled by the operating duty cycle and things work out so that D(Iin+Iout)=Iin.

If you control peak switch current then you are controlling peak (Iin+Iout). If you control average (integrated) switch current then you are controlling Iin. If you use a peak sensing method on the averaged switch current then you will get a peak to average error dependent on the amount of ripple.

You should be able to use an op-amp both as the integrator and error amplifier so you are truly controlling average switch current.

You can place your sense resistor in the ground return to the supply in which case you are properly sensing input current. The disadvantage is that that method includes the resonance resulting from the inductors and coupling capacitors which you are damping with your RC snubber across the main C. You get an extra pair of poles in the response.

If you include a source sense resistor then, ideally, it should not affect EMI.

DNA

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Genome

Here you go.....

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That controls input current.... it's not hysteretic, it's phase shift. You'll get the idea though.

DNA

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Reply to
Genome
[snip]

Ahh.....math integration of the switch current.. My integrator time delay point of view description probably came off too fuzzy..

The high side Isensing cct in my cuk design is to start the oscillation and to provide a soft start up.

Using your phase method would enable low side sensing electronics for Cuk starting.. I could try a phase method controlled start up and then let hysteretic control take over.... I'll do some sims and check it out.

Thanks for the asc...Certainly makes it clear... :) "A picture is worth a thousand words." D from BC

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D from BC

Nicely nicely then.

DNA

Reply to
Genome

Been searching too much and gave up looking for a CMOS 555 spice model on: TLC556 TLC555 TLC552 TLC551 LMC555

If I could, I'd try to modify the LTSPice subckt [1] to match data sheet specs..It just looks like a rats nest of nodes and parts and my spice knowledge is minimal. (Note: NE555 spec frequency is 500khz. CMOS timers are >2x faster.) I could make my own model from scratch... Takes up time :( There was an EDN article on doing that.

For my app, I need to model stuff like: Prop delay Reset logic levels depending on Vcc Internal resistor values (and this is sometimes missing on data sheets)

Not urgent, but would help...

[1] *** NE555 model supplied with LTSpice .subckt NE555 1 2 3 4 5 6 7 8 A1 N001 2 1 1 1 1 N003 1 SCHMITT Vt=0 Vh=1m R1 N001 1 5K R2 5 N001 5K R3 8 5 5K S1 1 7 N012 1 D A2 N006 N003 1 1 1 1 N004 1 SRFLOP Trise=100n tripdt=10n A3 6 5 1 1 1 1 N006 1 SCHMITT Vt=0 Vh=1m S2 8 3 N010 1 O S3 3 1 1 N010 O A6 1 N013 1 N004 1 1 N012 1 OR Ref=.5 Vlow=-1 Trise=100n R7 8 1 4K R9 2 1 1G R10 6 1 1G A4 1 N004 1 N013 1 N010 1 1 OR ref=.5 Vlow=-1 Trise=100n A5 4 1 1 1 1 N013 1 1 SCHMITT Vt=.7 Vh=1m I1 8 4 .4m load D1 4 1 DR .model D SW(Ron=6 Roff=.75G Vt=.5 Vh=-.4) .model O SW(Ron=6 Roff=1Meg Vt=0 Vh=-.8) .model DR D(Ron=150K Roff=1T Vfwd=1.6) .ends NE555 D from BC
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D from BC

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