Review this Goofy 555 Based SMPS Design

"D from BC" schrieb im Newsbeitrag news: snipped-for-privacy@4ax.com... | On 21 Jan 2007 23:38:42 -0800, snipped-for-privacy@sushi.com wrote: | | >Dell used to roll their own Dc/DC converters with 555s. Well, the key | >phrase is "used to." | | Do you know if it was hysteretic or PWM? | I recall seeing an app note one time for turning the 555 into a PWM. | D from BC

I guess I saw one in a Supertex SMPS app note.

- Henry

--

It's a feel-good kind of thing ;-)

...Jim Thompson

--
|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
|  Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
|  Phoenix, Arizona            Voice:(480)460-2350  |             |
|  E-mail Address at Website     Fax:(480)460-2142  |  Brass Rat  |
|       http://www.analog-innovations.com           |    1962     |
             
I love to cook with wine.      Sometimes I even put it in the food.

What advantage (apart from including a few resistors) do you get by using the C555s, instead of a dual comparator?

I had to pick one of the following methods:

• Schmitt inverter or schmitt gates

• Comparator with hysteresis control pin

• Positive feedback or feedback to a switch

• 2 comparators and a discrete SR latch

• CMOS 555

I had to pick something... I've never used the 555 this way before and I liked the newness factor. Besides..prop delay, I draw, Vs specs fit the app ok.

I posted about hysteresis methods some time ago. IIRC somebody bashed the positive feedback method in favor of the SR method.

I haven't done a study to compare the methods for an economic/performance fitting in my app. It was one of those "works....good enough...move on...." decisions. Also..it's hobby electronics...I can do artsy stuff like that :)

To really answer your question... I dunno... D from BC

news: snipped-for-privacy@4ax.com...

and if it finds, it executes del *.*

But I am using the LT op amps and might get suckered into using them.. :)

D from BC

Fair enough. Shouldn't you add a third C555 to control output voltage? Add a pulsed switch that adds enough load to take the current above and below the current limit on a regular basis, to see how well both voltage and current regulation work.

BTW, you don't need the resistors on the 555 outputs.

[snip]

This is a constant current type power supply. I probably have to add voltage feedback in case the output voltage gets crazy with no load. But not with another 555. Probably a zener/resistor to U2.

I'll be doing "jumpy" load regulation tests later on.. For now, it's good for a static resistive load. I did catch some literature about CPU's being powered up with hysteresis type controllers. Fast response to loading?

You probably saw the jpeg...The PDF has a mouse over note that mentions the 555 out resistors. I have to include those resistors in LTSpice to see the waveforms... It's cool to see the mode change from input current regulation to output current regulation.

I'm currently checking to see how sluggish of an op amp I can use in the high side cct. I can't get the LT1784 to sim for some reason.. This is to reduce Q1 dissipation. D from BC

(snip)

No. I have been playing with the simulation in LTspice. After I eliminated the 555 output resistors, I watched the two 555s trade off control by displaying the current into each discharge pin.

I'm new to this prog..At first I clicked like crazy on the output pins and nothing..So I placed the resistors... Might be some left over habit from Circuitmaker 2000 where pins often need to be connected. I checked with just drawing a piece of wire at the pin in LTSpice... Then I got the signal.. :) D from BC

When you put the curser directly over the pin, a clamp on current probe, with an arrow through it that shows the direction of a positive current should appear. Left click there, and a current trace should appear on the graph. This is especially handy if you are also graphing large voltage swings from other nodes, that make the low voltage pin trace very small. The current trace gets its own scale factor, on the right side of the graph.

"D from BC" schrieb im Newsbeitrag news: snipped-for-privacy@4ax.com... | On Mon, 22 Jan 2007 12:20:50 +0100, "Henry Kiefer" | wrote: | | >"D from BC" schrieb im Newsbeitrag news: snipped-for-privacy@4ax.com... | >| The ironic thing is LTSpice SwitchercadIII was probably made to sell | >| LT controllers but I'm controlling with cheapo 555's instead. | >

| >In the next version of LTspice Mike seeks for the string 555 in open documents and if it finds, it executes del *.* | >

| >Oh I forgot to add /s | >

| >Have fun! | >- Henry | | But I am using the LT op amps and might get suckered into using them.. | :)

Double check that no LT op amp type number includes 555 !

- Henry

--

Maybe you might know....

I'm trying to replace U1 with a lower a GBW op amp. This is to lower Q1 dissipation. Trying LT6221.

I'm absolutely stumped... There's some sort of breakdown effect but the timing is random in LTspice. Looks like very narrow HV "clicks" at the 555 U3 trigger input.

Is this for real? It doesn't happen with the 80Mhz GBW LT1800 op amp.

Notes:

1)Inductor parallel capacitance is estimated at 3pF. Added filter..Not it... 2) Using latest LTC.lib file from LT. 3) Tried LT1784, LT6237 ..same effect 4) Schematic on

D from BC

I don't think it is real, though you might want to eliminate the minimum time step in the tran setup and add a small capacitor across D1 (I used a .1u). That seems to get rid of the problem on this end.

You might do your experiments with the UniversalOpamp2 at the far end of the opamp list. It has completely programmable gain bandwidth, slew rate and phase margin so you can really find out where the limit is. Then you just have to find an opamp that exceeds the minimum performance.

[snip]

I got the fake "clicks" from the high side cct greatly reduced but not eliminated. Will ignore .....Something is probably different at my end. Great! I'll use that user defined opamp model... Thanks.

I'll be posting a new schematic when I get the following done:

1) HV linear regulator 2) Parts optimized for low power with respect to mos drive power dissipation. 3) Adding failsafe parts and bypassing

D from BC

cute

I wasn't involved in the study. As you probably know, most IC companies open up products to see who is using what. So more correctly I was told Dell was using 555 circuits.

There are so many things that can go wrong in DC/DC design that I can't ever see not using a real controller chip. Start up and undervoltage lockout can be a real headache.

This 555 based smps is a design challenge + LTSpice learning project...so I'm not sure if my question below is steering away from the "spirit" of sci.electronics.design..

I got the Zetex spice library... zmodels.lib. I copied and renamed a PMOS symbol file..That looks ok.

Now for the syntax editing? :(

I get this message in LTSpice: Error on line 2 : m1 0 n003 n002 n002 zmodels.lib zvp2120g Unable to find definition of model - default assumed

The Zetex library section:

*ZETEX ZVP2120G Spice Model v1.0 Last Revised 10/8/05

• .SUBCKT ZVP2120G 3 4 5

• D G S M1 13 20 5 5 Pmod1 RG 4 2 100 RIN 2 5 1E9 RL 3 5 1.2E8 RD 3 13 Rmod1 22 C1 2 5 55E-12

**C2 3 2 15E-12 D1 3 5 Dmod1 D2 3 17 Dmod2 Egs1 2 17 2 5 1 Egt1 2 20 5 21 1 Vgt1 5 22 1 Igt1 5 21 1 Rgt 21 22 Rmod2 1 .MODEL Pmod1 PMOS VTO=-2.8 RS=2 IS=1E-15 KP=0.17 +CBD=60E-12 PB=1 LAMBDA=6E-3 .MODEL Dmod1 D IS=5E-12 RS=2 BV=220 .MODEL Dmod2 D CJO=70e-12 IS=1e-30 N=10 .MODEL Rmod1 RES (TC1=4.5e-3 TC2=4E-5) .MODEL Rmod2 RES (TC1=-2.5e-3 TC2=3e-6) .ENDS ZVP2120G * *$

It's probably a dum question, but I'm afraid to burn too much time researching spice syntax differences.. How do I edit the ZVP2120 subckt so I can sim this Zetex PMOS? Links?

D from BC

I'm only a casual user of LTSpice, but I'd guess it's a device call issue....

The ZVP2120G is defined via a _SUBCKT_

Thus it must be called in the netlist:

XM1 0 N003 N002 N002 ZVP2120G ; NOTE the "X"

and you need the library...

.LIB Drive\\Path\\zmodels.lib

I've not seen calling the library in the same line as the device.

...Jim Thompson

--
|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
|  Analog/Mixed-Signal ASIC\'s and Discrete Systems  |    manus    |
|  Phoenix, Arizona            Voice:(480)460-2350  |             |
|  E-mail Address at Website     Fax:(480)460-2142  |  Brass Rat  |
|       http://www.analog-innovations.com           |    1962     |
             
I love to cook with wine.      Sometimes I even put it in the food.

Here's a possibly obscure problem...

I found the Zetex high side current monitor IC... What I can't figure out is how can I get offset current control? ...Preferably, without splitting the current path from the Iout pin with a constant current source. It's gotta be a high side adjustment. Expressed by math: Iout = Vsense*1.2/Rshunt - (Ioffset?) Or expressed: Iout = ACcurrent - DCcurrent(offset)

No internal schematic on the data sheet.

Or should I just drop that idea and stick with the op amp/transistor feedback combo ? R8 offsets Ir4 current by about 0.6mA. As seen on:

If I go with the Zetex IC; I'll use a cascode cct so as not to overvolt the IC. D from BC

Just in case.......

In a CUK converter the average switch current is the input current.(?) You might try a source sense resistor followed by an integrating op-amp stage to reconstruct a facsimile of the input current. Then you won't need high side sensing.

DNA