>>It might be amusing to suggest a class (SED lurkers) problem... design
> >>(at the CMOS transistor level) a three-input NAND, so that delays to
> >>output from each input are identical.
> Not just to satisfy equal delays... match paths, I care not the
> absolute delay for this question.
Got it. Twelve active devices, looks ugly. Uglier still when the outputs and inputs are buffered.