Well, the traditional three-NMOS-in-series, three-PMOS-in-parallel layout is equal, to a first approximation. If you want to count parasitic capacitance of each transistor to substrate, that will make things uglier, since the bottom NMOS has to discharge the two NMOS above it, plus all three PMOS and the wiring. Likewise, the rising edge becomes faster when 2 or 3 inputs are driven low simultaneously (PMOS working in parallel).
Tim