>>It might be amusing to suggest a class (SED lurkers) problem... design
>>>(at the CMOS transistor level) a three-input NAND, so that delays to
>>>output from each input are identical.
>>
>>Not enough data, I think...
>>JF
>
> Not just to satisfy equal delays... match paths, I care not the
> absolute delay for this question.
>
> It's a trick question (as if you didn't know ;-)
Well, the traditional three-NMOS-in-series, three-PMOS-in-parallel layout is equal, to a first approximation. If you want to count parasitic capacitance of each transistor to substrate, that will make things uglier, since the bottom NMOS has to discharge the two NMOS above it, plus all three PMOS and the wiring. Likewise, the rising edge becomes faster when 2 or 3 inputs are driven low simultaneously (PMOS working in parallel).
Tim