PWM Amp Design

"Chris Carlen" wrote in message news: snipped-for-privacy@news3.newsguy.com...

Salutation.

(A note for other readers: That is an H-bridge MOSFET switch without internal feedback and a near-linear optional sawtooth generator to help convert an input to PWM.)

max. into a load of unspecified resistance.

Specifying at least a range would help a lot. Does the load actually change once a system is built? Or do you just not know the load yet?

80V, but for any load resistance, the output

Is current limiting an issue? (I would think so if the load is as ill-behaved as you have allowed here.)

If phase delay up to 150 Hz is what you really care about, it would be more useful to know that requirement.

feeding into a simple integrating summing amp driving the

the output voltage sense is done prior to output

control.

I suggest that, with an appropriate controller, it would be fine to control the filter output instead. That would likely simplify getting the phase delay you want, by easing the derived and hence subsidiary requirements.

values of course needing to be tuned to the load

That makes me think the load may be knowable after all.

12.5kHz.

Is it a 2 pole LC LPF, nominally?

filter elements are 22.5uH and 7.2uF.

Is there any reason you cannot adjust the controller response to accomodate the load variation?

LC filter for the PWM becomes resonant with the added

The controller could provide the damping without the necessity of dissipation or extra HF output.

across the load.

That is a hit with respect to ripple.

near and above the crossover frequency of the load

and dissipating massive power. Up to about 115W at

EMI might suffer, too, depending on what the inductors really look like.

about 150Hz, so the 10kHz amplifier response is way

loop, so the wide band amp relative to the

With a controller designed to bring the LC LPF poles where they would help form a traditionally design, controlled phase-delay filter, I expect the difference between your desired passband and the switching frequency will make it an easy job.

approaches other than an equalizing network one might try

try to sense the PWM output post-filter, and then

Glad you are open to this.

I don't know about typical. I've done exactly that for a system with much less separation between the intended signal band and the switching frequency.

train is inadequate. I am aware of the state space

plane zero in these circuits.

The simple PWM with bridge does not have the RHP zero and its response is quite consistent as long as the initial filter inductors do saturate and the input supply is relatively stable.

correct model for my PWM amp before I can attempt

The response is very simple. The transfer function is a constant once the switching frequency is taken out. Write a few expressions for the steady state DC output versus duty cycle and see for yourself.

control might be to eliminate the overshoot inherent in

response as well).

Yes.

the load impedance, and if there is substantial load

waste power or complicate the compensation required.

That would depend on how far the poles are moved by the controller relative to the variation in their open loop positions due to load variation. I do not see an inherent problem, depending on your final accuracy requirements.

they are ripple free, but in this case I opted for

and bunch of other CPU type electronics in a 7" high

amps.

Given your requirements, PWM with appropriate feedback and control seems like a good choice.

You're most welcome.

--
--Larry Brasfield
email: donotspam_larry_brasfield@hotmail.com
Above views may belong only to me.

My idea was that since I had to build an amp for about 3.5A RMS into the load of 2.5ohm+250uH for a specific application in which the load will never change, that I might use the opportunity to make a somewhat more generalized hardware foundation which could be used for similar applications in the future with different loads. Hence the "unspecified" load. Reasonably speaking, we would be considering mostly slightly inductive loads such as motors and solenoids ranging from perhaps 0.5-20ohms, and 10-1000uH. I doubled the current capability from my application's 3.5A RMS (but must be able to deliver 10A peak currents anyway, so the filter inductors mustn't go flat at that current) to 7A just for flexibility.

At this point, current limit isn't necessary. I don't like being unprotected from short circuit, but the complexity of implementing this vs. the timeframe for getting something running (this is an experimental lab apparatus application, not a commercial product) forces me to implement the simplest approach first. I can spend time on refinements later.

Current limiting would also be complicated by the fact that we need to be able to deliver accelerating currents of 10A to perhaps even the SA60's 15A peak capability, which the load coils can handle briefly, but not continuously. So a current limit designed to protect the load would have to allow short bursts of high current, but somehow take into account the average power limitations of the load as well as its transient thermal limitations.

2 degrees.

Yes.

There is no load variation in this case. The response would have to be adjusted for different load applications.

That would be cool (in more ways than one.)

Huh? Wouldn't crossover of load current at high frequency to the capacitive branch actually reduce ripple? Oh wait, or does it modify the filter response so as to reduce the cutoff slope? No! That's the point of the equalization, to present to the filter an effective resistive load of 2.5 ohms at all frequencies. But from the real load's perspective...it sees its current dropping off as its own inductance kicks in. Actually, since the voltage across both the real load and the capacitive branch are the same, I don't think there is any effect on ripple. I'll have to check this.

Do you mean because they are having to conduct the full current expected from a resistive load at the cutoff freq. whereas if there was no capacitive equalizer, then their current thus radiated mag. field would drop off more quickly at HF?

Hmm.

That's a good sign.

Saturate? Why would we want that? Perhaps you mean "don't saturate?"

They will be designed to hold up at least 75% of their inductance to 10A.

Yes, I have already done this. Quite a while ago I did a sim where it seemed things *didn't* work with this model, but did work in reality. Kind of backwards from what usually happens. I thought because my AC model was missing the RHP. Perhaps you are correct. Now the other day I discovered that maybe my model wasn't so broke after all. I haven't pursued it very thoroughly because I knew I could get away with a simple integrator and "turn the knobs until it works" design based on the simple topology in Apex's app note AN33. But I hate to design things that way. Like I said, we need a result and I have already gotten burned once in this project for spending too much time making sure things worked theoretically, while some other guy just empirically tinkered his way to a working result (that's referring to the outer control loop in which this amplifier will fit).

I need to spend some more time with pencil and paper to understand how the controller can "move the poles" of the filter. I think you mean that the closed loop transfer function will have it's poles not in the same place as the open loop right? So far I haven't dealt with any cases of having complex poles in the open loop, so this is virgin territory.

Yes, a linear amp would have needed water cooling to fit in the desired package.

Thanks for the input.

Good day!

--
_____________________
Christopher R. Carlen
crobc@bogus-remove-me.sbcglobal.net
SuSE 9.1 Linux 2.6.5

of 2.5ohm+250uH for a specific application in which

somewhat more generalized hardware foundation which could

the "unspecified" load. Reasonably speaking, we would

ranging from perhaps 0.5-20ohms, and 10-1000uH. I

able to deliver 10A peak currents anyway, so the filter

Great. That makes the controller design a lot easier since it can be revised (but only slightly) for subsequent applications.

from short circuit, but the complexity of

experimental lab apparatus application, not a

spend time on refinements later.

I would think it could be added later without much interaction with the basic system. (There could be control issues, of course, in whatever outer loop this PWM+mover ends up in.)

to deliver accelerating currents of 10A to perhaps

but not continuously. So a current limit designed

somehow take into account the average power limitations

I suppose I can translate that to flat delay within +/- 37 uS from DC to 150 Hz and beyond that, don't care.

That, too, simplifies the controller and the math (if any) behind it.

adjusted for different load applications.

May I presume you are willing to use a 10% ceramic cap and 5% gapped core set for the inductor? (This may well be relaxed once the phase delay performance is simulated or analyzed with respect to sensitivity.)

I've always liked electronic damping.

branch actually reduce ripple? Oh wait, or does it

point of the equalization, to present to the filter

load's perspective...it sees its current dropping

the real load and the capacitive branch are the same,

Perhaps I misread your statement. I took it as (a 2.5ohm resistor in series with a 40uF capacitor) across the load whereas you apparently meant a 2.5ohm resistor in series with (a 40uF capacitor across the load). At any rate, I would get rid of the resistor, except for a residual to be used for current sensing later.

a resistive load at the cutoff freq. whereas if

would drop off more quickly at HF?

I mean because of my misunderstanding of your network.

warranted. (Actually, perhaps only about 3kHz might

Having sketched a quick root-locus for this, I am still convinced. I have two complex poles in G, near the imaginary axis, and two zeros in H near the real axis and about as far from the origin as the LPF poles. (And some poles way to the left to make it realizable.) With the right loop gain, the poles move to the left and around the zero pair, ending up just about wherever they are most useful for that controlled delay filter I mentioned.

What kind of DC accuracy do you need? Can gain variation induced by 80V supply variation be handled by an outer loop? Or does this power amp have to have very tight gain and offset specs? (Until it appears necessary, I hesitate to add a pole at zero just to reduce maybe tolerable error.)

the peaking within the PWM amplifier control loop.

That was a bit of a challenge, but your task is enough easier that I wanted to offer that encouragement.

other models which correctly predict the presence of

Yes. (I don't know why proof-reading is so hard.)

Gapped parts would do better. If the open-loop response can be kept more predictable, it will be easier to control the close-loop phase delay. The LC poles do not have to be kept so far out.

I should have said "for the quasi-steady-state from one cycle to another". The DC case is trivial and not of much use for a transfer function. The method I prefer, for fixed switching frequency, is to analyze cycle to cycle increments as a function of duty cycle and translate those to equivalent derivatives.

things *didn't* work with this model, but did work

AC model was missing the RHP. Perhaps you are

As long as the H-bridge switches are always on, either one way or the other, (and the inductor is constant!), it really is that simple. You can think of the bridge as simply a "DC" signal with some AC on it. (There is also a delay, on the order of a partial cycle, but that can be ignored when you are willing to filter off the AC anyway.) The "DC" part is just the mean as affected by duty cycle.

I haven't pursued it very thoroughly because I knew

design based on the simple topology in Apex's app

Two poles near the imaginary axis plus one at

0 is a formula for something that either oscillates or is very poorly damped.

have already gotten burned once in this project for

other guy just empirically tinkered his way to a

amplifier will fit).

I'd like to see him empirically stabilize a rocket. (But from quite a distance.)

that additional compensating measures must be taken

controller can "move the poles" of the filter. I think

the same place as the open loop right?

Yes. As long as there is some loop gain, the poles are shifted from their open-loop positions.

loop, so this is virgin territory.

That's were it becomes fun. With a few more answers, I am inclined to simulate a controller and idealization of your plant.

package.

You're welcome, and likewise.

--
--Larry Brasfield
email: donotspam_larry_brasfield@hotmail.com
Above views may belong only to me.

Sounds like something I designed a few years back (with less power output though) for an induction loop amplifier. The compensation filter is a pain in the ass where it comes to dissipation.

Did you look into:

This device seems a lot more rugged and complete than the SA60 chip. Despite the lesser specs, I think it will still do well for the project you're working on. One of the advantages is that the TDA8924 can work with much higher frequencies which makes the output filter easier to build (as you can see from the sample diagram). If EMI is a concern, you can use a common mode filter between the output and the load.

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"Larry Brasfield" wrote in message news:pwT5e.13$ snipped-for-privacy@news.uswest.net...

....

of 2.5ohm+250uH ....

[re phase delay up to 150 Hz]

....

....

....

The design is not very sensitive considering the fairly wide group delay band that is apparently allowed. The above accuracy is likely to be excessive.

....

Upon further reflection, an integrator in the forward path to get precise gain and offset is no big deal. With a little tweaking to get the 3 poles properly related to each other, the group delay easily falls within a couple uS band out to 400 Hz. With even more effort, (ajusting the zero positions and care in setting loop gain), the 3 poles could be made to conform to a cookbook equiripple group delay LPF. From the initial results of simulation, I see no need to bother with that mathematical exercise.

....

For the simulation included below, I set the LC poles about 10 times closer to the origin, similar damping. This should take down the ripple most of 40 dB. It can work to set the filter higher, but the shifted poles get closer to the switching frequency than I would like to see.

loop, so this is virgin territory.

Following is source for an LTSPice simulation (see

) with the 2 zeroes and 1 pole in H, and 1 pole at 0) in G. This is not any kind of final design, but it does demonstrate how easy it will be to attain the performance so far mentioned. For a real circuit, there may need to be a bit more filtering to keep switching junk out of the first near-differentiator (or it may be fine as is). It will certainly work to use slower op-amps.

========== begin lcyank.asc ============== Version 4 SHEET 1 880 740 WIRE -528 496 -528 448 WIRE -512 240 -512 224 WIRE -512 336 -512 320 WIRE -496 448 -528 448 WIRE -496 528 -496 448 WIRE -480 448 -496 448 WIRE -480 528 -496 528 WIRE -432 224 -512 224 WIRE -432 240 -432 224 WIRE -432 336 -432 320 WIRE -368 448 -400 448 WIRE -368 528 -400 528 WIRE -352 448 -368 448 WIRE -352 528 -368 528 WIRE -336 224 -432 224 WIRE -256 320 -256 224 WIRE -256 496 -256 352 WIRE -240 320 -256 320 WIRE -240 352 -256 352 WIRE -224 224 -256 224 WIRE -144 224 -160 224 WIRE -144 336 -176 336 WIRE -144 336 -144 224 WIRE -96 336 -144 336 WIRE -80 336 -96 336 WIRE -80 496 -256 496 WIRE -80 496 -80 384 WIRE -64 496 -80 496 WIRE -32 192 -32 176 WIRE -32 288 -32 272 WIRE 16 176 -32 176 WIRE 16 384 0 384 WIRE 16 480 0 480 WIRE 16 480 16 384 WIRE 32 480 16 480 WIRE 32 512 0 512 WIRE 32 544 32 512 WIRE 48 176 16 176 WIRE 64 384 16 384 WIRE 144 480 112 480 WIRE 160 176 128 176 WIRE 160 240 160 176 WIRE 160 320 160 304 WIRE 192 176 160 176 WIRE 208 176 192 176 WIRE 208 384 144 384 WIRE 208 384 208 176 WIRE 208 480 208 384 WIRE 256 176 208 176 WIRE 256 192 256 176 WIRE 256 304 256 272 WIRE 256 400 256 384 FLAG -512 336 0 FLAG -32 288 0 FLAG 256 400 0 FLAG 160 320 0 FLAG -528 496 0 FLAG -368 448 VP FLAG -208 304 VP FLAG -32 464 VP FLAG -368 528 VN FLAG -32 528 VN FLAG -208 368 VN FLAG -432 224 VS FLAG 192 176 VX FLAG 16 176 VA FLAG -96 336 VC FLAG -432 336 0 FLAG 32 544 0 SYMBOL res 240 288 R0 SYMATTR InstName R1 SYMATTR Value 2.5 SYMBOL ind 240 176 R0 SYMATTR InstName L1 SYMATTR Value 250? SYMBOL cap 144 240 R0 WINDOW 0 7 -9 Right 0 WINDOW 3 -7 24 Right 0 SYMATTR InstName C1 SYMATTR Value {7.2?/LPFS} SYMBOL ind 32 192 R270 WINDOW 0 32 56 VTop 0 WINDOW 3 5 56 VBottom 0 SYMATTR InstName L2 SYMATTR Value {22.5?/LPFS} SYMBOL OpampsLT1215 -32 432 M0 SYMATTR InstName U1 SYMBOL OpampsLT1215 -208 272 R0 SYMATTR InstName U2 SYMBOL bv -32 176 R0 WINDOW 3 30 -75 Left 0 SYMATTR InstName B1 SYMATTR Value V={GX*V(VC)} SYMBOL voltage -512 224 R0 WINDOW 123 -25 94 Right 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V1 SYMATTR Value 0 SYMATTR Value2 AC 1 SYMBOL voltage -384 448 R90 WINDOW 0 -14 103 VBottom 0 WINDOW 3 4 10 VTop 0 SYMATTR InstName V2 SYMATTR Value 10 SYMBOL voltage -496 528 R270 WINDOW 0 -32 10 VTop 0 WINDOW 3 -4 100 VBottom 0 SYMATTR InstName V3 SYMATTR Value 10 SYMBOL res -448 224 R0 SYMATTR InstName R2 SYMATTR Value 12k SYMBOL cap 144 496 R270 WINDOW 0 32 32 VTop 0 WINDOW 3 0 32 VBottom 0 SYMATTR InstName C2 SYMATTR Value 1n SYMBOL res 160 368 R90 WINDOW 0 -4 71 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R3 SYMATTR Value 12k SYMBOL res 16 368 R90 WINDOW 0 11 19 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R4 SYMATTR Value 12k SYMBOL cap -160 240 M270 WINDOW 0 23 7 VTop 0 WINDOW 3 0 32 VBottom 0 SYMATTR InstName C3 SYMATTR Value 1n SYMBOL res -352 208 M90 WINDOW 0 -3 73 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R5 SYMATTR Value 12k SYMBOL res 128 464 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R6 SYMATTR Value 1k TEXT -204 606 Left 0 !.ac oct 20 10 500k TEXT -496 96 Left 0 !.step param GX 0 5 1 TEXT -496 128 Left 0 !.param LPFS=.1 ========== end lcyank.asc ==============

The above simulation should be a convincing demonstration that using the controller to get the PWM filtered output response apparently desired by the OP is feasable and unlikely to present serious problems. Obviously, gains and maybe offsets will need adjustment once the VCVS is replaced by the PWM IC. When current limiting is put into place, some attention to limiting in the controller will be in order. A sensitivity analysis for L and C variation would be smart. It might be a good idea to make sure no limit cycles are possible, using time domain simulation and a range of step inputs.

--
--Larry Brasfield
email: donotspam_larry_brasfield@hotmail.com
Above views may belong only to me.

I read in sci.electronics.design that Nico Coesel wrote (in ) about 'PWM Amp Design', on Sun, 10 Apr 2005:

You put a Zobel network (series RC) across the loop? There is a much better solution described in BS 7594, using a series capacitor and one or two resistors. But these days, there is usually no reason not to use a current-drive amplifier.

--
Regards, John Woodgate, OOO - Own Opinions Only.
There are two sides to every question, except
'What is a Moebius strip?'
http://www.jmwa.demon.co.uk Also see http://www.isce.org.uk

I used a Zobel network indeed (I more or less followed the HIP4080 appnote). But when it comes to class D amplifiers I came to the conclusion that trying to make a perfect filter network using bessel or butterworth is a futile excercise. The inductor and capacitor values will vary too much because of the changing currents and voltages.

Also, a zobel filter depends highly on the load, so you would need to fit a different filter for every application or make it adjustable. In case of a induction loop amplifier, the number of tables and chairs and their location in the room would enter the equation :-))

In other words, butterworth, bessel and zobel look nice in theory, but their practical use is very limited when it comes to class D amplifiers.

I found out that using some inductors and capacitors to smear the pulses into something that looks like a signal and using a common mode filter as a final stage to get rid of the HF components works much better.

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One can incorporate any number of LC output filter sections within the feedback loop of an amplifier. Doing this requires sensing a more or less orthogonal set of states for the output filter and delivering them in a properly weighted measure of feedback and feedforward terms to the error amplifier. Here is a link to my illustrated explanation of this technique: (You may have to become our newest group member to access this file :) ...it's free to join.)

Do you have access to the binaries group? I could also post the PDF there as well. In any case, here is the text sans illustrations:

The ?Leapfrog? Method Of Switching Amplifier Control Loop Design snipped-for-privacy@ieee.org - 1996

The leapfrog design method extends active damping techniques to incorporate an unlimited number of output filter sections within a switching amplifier feedback loop. By working in steps from the power switching stage outward, the process of designing gain coefficients for each feedback filter component is simplified to a first order problem. At each stage the amplifier?s impedance characteristic leapfrogs between that of current and voltage source (hence the name). The leapfrog method breaks the design problem into manageable steps, and turns what would otherwise be a practically intractable problem with four, six or more independent variables, into a series of straight­forward choices for each feedback coefficient.

Switching amplifiers are attractive for high power audio applications because of their inherently low conduction/blocking losses. This results from maintaining the output power devices in either a fully saturated or cut-off state such that they never simultaneously support large currents and voltages as is typical of standard linear audio amplifiers. This switching characteristic can provide an important efficiency advantage over standard linear amplifiers if the losses from the switching transitions are also kept to a relatively low level. Toward this end it is desirable to switch at as low of a frequency as is compatible with closed-loop system bandwidth and output impedance requirements (a switching amplifier is actually a high level digital sampled data system with its ensuing Nyquist sampling effects which limit maximum bandwidth to no more than one half the switching frequency).

Another significant complication often arises because of the need to strictly limit the level of switching ripple components on the amplifier?s output without restricting the amplifiers ability to deliver rail-to-rail audio signals at 20 kHz. This requires the use of an output recovery filter with multiple L/C sections and with pole locations just above the audio pass band. To optimize closed-loop system bandwidth and output impedance necessitates that the feedback system be able to track and compensate the rapid phase shift stemming from the output filter?s high Q poles and zeros, the location of which will vary dynamically due to current and temperature dependent shifting of the component values. Note that, in high efficiency power applications, dissipative elements may not be readily used in the recovery filter to control L/C resonances.

This has not been an easy problem to solve using traditional tech- niques. Standard compensation methods with op­amps, resistors and capacitors fail because it is not possible to match and track the frequency characteristics of the high Q L/C filter sections. Typically, the amplifier?s feedback loop will include none or only the first of the output filter sections within its control loop. This approach degrades the accuracy of the amplified audio signal.

In some prior switching amplifiers, the control loop has been designed using active damping techniques to track filter component shifts, manage output filter Q and extend bandwidth. With this method, a sensed signal directly proportional to output filter capacitor current is an integral part of the feedback loop. This ensures direct, accurate tracking and control of output filter resonances, and allows maximum loop gain-bandwidth in the face of a single L/C filter section.

The leapfrog design method described below extends the active damping technique to incorporate an unlimited number of output filter sections within the feedback loop, and describes how to choose the gain coefficients for each feedback filter component by working in steps from the power switching stage outward. As the gain coefficient for each component is chosen, and that component is incorporated within the amplifier?s black box boundary, the impedance characteristic the amplifier presents at its output changes to a current source if the component is an inductor or to a voltage source if the incorporated component is a capacitor. As each component is swallowed up, the overall closed loop bandwidth must be reduced by a small factor (about

1.5 or so). Thus, the amplifier?s output characteristic leapfrogs between that of a current and voltage source (hence the name). This simplifies the design process of each succeeding gain coefficient to a first order problem. The leapfrog method breaks the design problem into manageable steps, and turns what would otherwise be a practically intractable problem with four, six or more independent variables, into a series of straight­forward choices for each feedback coefficient.

The figure below will be used to illustrate the leapfrog design process for a four-element ladder filter network. Working from the power switch to the output (left to right), the voltage command to the power stage/modulator is the sum of the positive feedback signal of the voltage appearing on the output side of L1 and the negative feedback signal of the inductor current. Note that the modulator and totem pole output stage is approximated as a voltage controlled voltage source with delay due to sampled data nature of the pulse width modulation process. The unity gain positive feedback term of the load side voltage from the inductor serves to keep the voltage across the inductor (and hence its current) constant in the face of load side voltage perturbations. The negative feedback signal of inductor current roles off with a single pole due to the rising impedance of inductor L1. Gain K1 is set so that loop gain falls to zero somewhat before half the switching frequency (where the switching delay adds 180 degrees phase shift). As the inductor is merged into the black box of the amplifier on the left hand side, the resulting equivalent voltage controlled current source is shown below feeding the next filter element C2.

Next, capacitor C2 is incorporated into the equivalent circuit in exactly a dual nature. Looking at the following figure, the unity gain positive feedback term of load side current out of the capacitor functions to null net current through the capacitor in spite of sudden changes in load current, minimizing the resulting voltage fluctuations. The negative feed­back term of capacitor voltage roles off with a single pole due to the falling impedance that capacitor C2 presents to the controlled current source. Gain K2 for this feedback path is set so that loop gain falls to zero at about two thirds of the current source?s bandwidth. The resulting equivalent voltage controlled voltage source is shown below feeding the next filter element L3.

Now the leapfrog method has come full circle to the starting conditions of a controlled voltage source feeding an inductor element in an LC filter ladder. Just as before, this element is incorporated into the system by applying the appropriate amounts of positive and negative feedback. Gain K3 for this feedback path is set so that closed loop gain is about two thirds of what it was before. The resulting equivalent voltage controlled current source is shown below feeding the next filter element C4.

The process continues until all the filter elements are incorporated into the amplifier, yielding a well controlled, component insensitive, switching amplifier with the maximum possible bandwidth. These advantages come at a cost of an extensive feedback network distributed throughout the switching amplifier?s recovery filter ladder.

In practice, both the sensing and feedback amplifier circuitry can be greatly simplified by combining adjacent signal paths. In particular, combining stages removes the need to reproduce dc signals in the sensing circuitry. Recognizing that the difference of inductor currents must flow through the capacitor on the common node between adjacent stages justifies using a simple current transformer to sense this difference current. Likewise, recognizing that the difference of capacitor voltages must appear across the interposing inductor justifies using a simple floating winding to sense the difference voltage.

All of the distributed gain terms are easily consolidated into a single summing amplifier by simply accounting for the cumulative gain terms in the path for each signal as shown above.

Following these constructs results in a switching amplifier system that is both practical and simple, yet easily accommodates a recovery ladder filter network of any length within its feedback path.

The following schematics were simulated in LTspice in order to demonstrate and confirm the principles of the leapfrog method of switching amplifier design. As expected, the simulation output from the three variations was absolutely identical, verifying the validity of the topological manipulations.

Typical output from ac frequency response and 10kHz square wave transient response is presented below, with each showing the effect of stepping the load resistor from 1 to 8 ohms. Note that fs represents the effective sampling frequency which may be quite different from the nominal switching frequency. For example, in a free-running, self- oscillating design, the effective sampling frequency would be very close to the lowest switching frequency during dynamic excursions and not the typically 3-to-4-times higher quiescent operating frequency. Likewise td represents the effective worst-case delay rather than the typical delay. Thus, the rather high fs and low td of the simulation would be difficult to achieve in practice unless the design employed multiple, parallel, staggered phase output stages feeding the recovery filter. (This technique multiplies the sampling frequency by the number of staggered phase output stages.)

Chris Carlen wrote:

At the end of this post is an LTspice schematic files that is an example of a large signal frequency response analysis of a class d amplifier.

This simulation uses the recently derived* mathematically correct swept sine time domain source in conjunction with a very fast running LTspice A-device to analyze the large signal behavior of a self oscillating class d amplifier under a variety of dc bias levels (approximates high frequencies riding on a large bass signal). The sine source is swept logarithmically from 2.5kHz to 250kHz (25kHz is center screen).

Many weird large signal effects (such as frequency shift, aliasing, pulling and lock) are clearly visible. Note that none of these would be evident in a small signal ac analysis.

When properly set up, the A-device simulates a realistic delay while efficiently allowing maximum step size between switching edges and simultaneously capturing edge timing with great fidelity. This makes successive design iterations possible with almost no waiting. :)

Regards -- analog

*Earlier (in the LTspice Yahoo Group) I was trying to generate a logarithmically swept sine source that would produce the equivalent of a small signal linearized frequency-based ac analysis in a time domain-based transient analysis. My intuition had led me to expect that given a slow enough sweep, the "doppler effect" on the swept sine wave should have been small enough to ignore.

The sort of .tran swept sine source I was seeking would allow direct frequency response analysis of such non linear circuits as switching power supplies or class D amplifiers without having to replace them with "equivalent" linear models.

I am fortunate enough to have a good personal friend (known as "The Phantom" on sci.electronics.design, etc.) who is both an excellent analog engineer and a wizard with Mathmatica. With his assistance I now have an exact expression for a logarithmically swept sine wave source in the time domain. This technique makes a *very* nice addition to LTspice's burgeoning tool set.

Here are the basic equations:

The sine wave: V(t) = Vp*sin(2*pi*f*t); f normally constant

The sweep function: f(t) = f1*(f2/f1)**(t/dt); where f1 is the start frequency f2 is the stop frequency dt is the sweep duration

As noted, simply combining the two equations squeezes the resulting sine wave, leading to frequency "compression".

V(t) = Vp*sin(2*pi*f1*(f2/f1)**(t/dt)*t); WRONG!!

Here is the correct form:

V(t) = Vp*sin(2*pi*f1*(f2/f1)**(t/dt)*dt/ln(f2/f1)); mmm..good

~~~~ UcD_swept_sine_test.asc (cut&paste & mind the word wrap) ~~~~ Version 4 SHEET 1 1324 680 WIRE 64 16 64 -64 WIRE 64 128 64 96 WIRE 64 256 64 224 WIRE 64 368 64 336 WIRE 96 -64 64 -64 WIRE 96 224 64 224 WIRE 112 -64 96 -64 WIRE 112 224 96 224 WIRE 224 -64 192 -64 WIRE 224 -64 224 -160 WIRE 240 -160 224 -160 WIRE 256 -64 224 -64 WIRE 256 16 256 -64 WIRE 256 32 256 16 WIRE 256 128 256 96 WIRE 288 -64 256 -64 WIRE 336 -160 320 -160 WIRE 368 16 256 16 WIRE 416 -160 400 -160 WIRE 416 -64 368 -64 WIRE 416 -64 416 -160 WIRE 480 16 432 16 WIRE 544 16 480 16 WIRE 656 16 624 16 WIRE 656 32 656 16 WIRE 656 128 656 96 WIRE 704 16 656 16 WIRE 752 -64 416 -64 WIRE 752 16 704 16 WIRE 752 16 752 -64 WIRE 752 32 752 16 WIRE 752 128 752 112 FLAG 96 -64 i FLAG 96 224 f FLAG 64 368 0 FLAG 64 128 0 FLAG 656 128 0 FLAG 752 128 0 FLAG 480 16 x FLAG 704 16 o FLAG 256 128 0 SYMBOL bv 64 240 R0 WINDOW 3 -24 168 Left 0 SYMATTR Value V=f1*{f2/f1}**(time/Td) SYMATTR InstName Bf SYMBOL bv 64 0 R0 WINDOW 3 -24 168 Left 0 WINDOW 123 -66 214 Left 0 SYMATTR Value V=Vdc+Vp*sin({2*pi*Td/ln(f2/f1)*f1}*{f2/f1}**(time/Td)) SYMATTR InstName Bi SYMBOL ind 528 32 R270 WINDOW 0 32 56 VTop 0 WINDOW 3 5 56 VBottom 0 SYMATTR InstName Lo SYMATTR Value 30µ SYMATTR SpiceLine Rser=10m Rpar=10k SYMBOL cap 640 32 R0 SYMATTR InstName Co SYMATTR Value 680n SYMBOL res 736 16 R0 SYMATTR InstName Ro SYMATTR Value 6 SYMBOL res 208 -80 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R2 SYMATTR Value 1k8 SYMBOL res 384 -80 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R1 SYMATTR Value 8k2 SYMBOL res 336 -176 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R3 SYMATTR Value 1k0 SYMBOL cap 400 -176 R90 WINDOW 0 0 32 VBottom 0 WINDOW 3 32 32 VTop 0 SYMATTR InstName C1 SYMATTR Value 150p SYMBOL cap 240 32 R0 SYMATTR InstName C2 SYMATTR Value 33p SYMBOL Digitalinv 368 -48 R0 WINDOW 3 0 112 Left 0 WINDOW 123 0 144 Left 0 WINDOW 39 0 176 Left 0 SYMATTR Value tripdt=1n td=200n SYMATTR Value2 Cout=33n Rout=10m SYMATTR SpiceLine Vhigh=45 Vlow=-45 SYMATTR InstName A2 TEXT 368 384 Left 0 !.tran 0 {Td} 10u uic TEXT 248 320 Left 0 !.param Vdc=0 Vp=1 f1=2k5 f2=250k Td=4m TEXT 472 -224 Left 0 ;To plot frequency on thenhorizontal axis changenthe quantity plotted ton"V(f)*1Hz/1V" and clickn"Logarithmic" TEXT 704 -32 Center 0 ;35kHz TEXT 480 -32 Center 0 ;400kHz TEXT 64 -336 Left 0 ;This circuit demonstrates the use of a swept sine source to test nthe large signal frequency response of an idealized UcD180 style nself oscillatiing class D amplifier, as a function of input amplitude,ninput offset, and output load. TEXT 256 232 Left 0 ;Sweep Parameters:nf1 = start freq f2= stop freq Td = sweep durationnVp = sine peak Vdc = sine offset TEXT 408 -392 Center 0 ;Swept Sine Analysis - analogspiceman 2005 TEXT 248 352 Left 0 !.step param Vdc list 0 -4 -8 RECTANGLE Normal 672 -368 144 -416 1

Whoops! Can't see the forest for the trees... I forgot to mention that the main point of the above is that it shows a design approach that incorporates the LC output filter within the feedback loop as an integral part of its self oscillating mechanism (note that this method is problematic if fixed frequency operation is required whereas the leapfrog method mentioned in an earlier post is perfectly general in this regard). -- analog

Chris Carlen wrote:

Here's an example of a self oscillating class d amplifier 'a la the leapfrog method that both contains the output filter within its feedback loop and provides integral output current limiting:

~~~~ ClassD_LeapFrog_UcD.asc (cut&paste & mind the word wrap) ~~~~ Version 4 SHEET 1 1328 1060 WIRE -1152 -112 -1152 -208 WIRE -1152 -32 -1152 -112 WIRE -1152 112 -1152 80 WIRE -1152 208 -1152 192 WIRE -1136 80 -1152 80 WIRE -1120 -208 -1152 -208 WIRE -1120 -112 -1152 -112 WIRE -1120 -32 -1152 -32 WIRE -1120 0 -1136 0 WIRE -1008 -208 -1040 -208 WIRE -1008 -112 -1040 -112 WIRE -1008 -16 -1056 -16 WIRE -1008 -16 -1008 -112 WIRE -976 -16 -1008 -16 WIRE -976 80 -992 80 WIRE -864 -144 -864 -160 WIRE -864 -64 -864 -80 WIRE -864 -16 -896 -16 WIRE -864 -16 -864 -64 WIRE -864 32 -864 -16 WIRE -864 80 -896 80 WIRE -864 80 -864 32 WIRE -864 128 -864 80 WIRE -864 208 -864 128 WIRE -832 -160 -864 -160 WIRE -832 -64 -864 -64 WIRE -832 32 -864 32 WIRE -832 128 -864 128 WIRE -832 208 -864 208 WIRE -832 240 -848 240 WIRE -720 -160 -752 -160 WIRE -720 -64 -752 -64 WIRE -720 -64 -720 -160 WIRE -720 32 -752 32 WIRE -720 128 -752 128 WIRE -720 128 -720 32 WIRE -720 224 -768 224 WIRE -720 224 -720 128 WIRE -688 -160 -720 -160 WIRE -688 32 -720 32 WIRE -576 32 -608 32 WIRE -576 64 -576 32 WIRE -576 160 -576 128 WIRE -560 32 -576 32 WIRE -496 -16 -496 -48 WIRE -496 128 -496 80 WIRE -496 224 -496 128 WIRE -496 400 -496 224 WIRE -496 480 -496 400 WIRE -496 640 -496 576 WIRE -480 400 -496 400 WIRE -416 128 -496 128 WIRE -416 224 -496 224 WIRE -416 352 -416 320 WIRE -416 528 -432 528 WIRE -416 528 -416 448 WIRE -384 -160 -384 -192 WIRE -384 -48 -496 -48 WIRE -384 -48 -384 -80 WIRE -384 528 -416 528 WIRE -384 544 -384 528 WIRE -384 640 -496 640 WIRE -384 640 -384 624 WIRE -352 352 -352 288 WIRE -352 528 -384 528 WIRE -352 528 -352 448 WIRE -336 528 -352 528 WIRE -272 -48 -384 -48 WIRE -272 -16 -272 -48 WIRE -272 128 -352 128 WIRE -272 128 -272 80 WIRE -272 224 -352 224 WIRE -272 224 -272 128 WIRE -272 400 -288 400 WIRE -272 400 -272 224 WIRE -272 480 -272 400 WIRE -272 640 -384 640 WIRE -272 640 -272 576 WIRE -192 32 -208 32 WIRE -192 64 -192 32 WIRE -192 160 -192 128 WIRE -112 288 -352 288 WIRE -112 288 -112 -64 WIRE -112 320 -416 320 WIRE -112 432 -112 320 WIRE -64 144 -64 -256 WIRE -64 160 -64 144 WIRE -64 240 -64 224 WIRE -64 496 -64 240 WIRE -64 640 -272 640 WIRE -64 640 -64 576 WIRE -32 32 -192 32 WIRE 32 -256 -64 -256 WIRE 32 -240 32 -256 WIRE 32 -144 32 -160 WIRE 32 -64 -112 -64 WIRE 32 -64 32 -144 WIRE 32 240 -64 240 WIRE 32 256 32 240 WIRE 32 352 32 336 WIRE 32 432 -112 432 WIRE 32 432 32 352 WIRE 48 -64 32 -64 WIRE 48 432 32 432 WIRE 64 -144 32 -144 WIRE 64 352 32 352 WIRE 80 32 48 32 WIRE 96 144 -64 144 WIRE 112 240 32 240 WIRE 128 -256 32 -256 WIRE 128 -192 128 -256 WIRE 128 -64 112 -64 WIRE 128 -64 128 -96 WIRE 128 240 112 240 WIRE 128 304 128 240 WIRE 128 432 112 432 WIRE 128 432 128 400 WIRE 144 -64 128 -64 WIRE 144 432 128 432 WIRE 240 -64 224 -64 WIRE 240 32 240 -64 WIRE 240 48 240 32 WIRE 240 144 160 144 WIRE 240 144 240 128 WIRE 240 432 224 432 WIRE 240 528 240 432 WIRE 240 544 240 528 WIRE 240 640 -64 640 WIRE 240 640 240 624 WIRE 256 -64 240 -64 WIRE 256 432 240 432 WIRE 272 32 240 32 WIRE 272 528 240 528 WIRE 336 -64 320 -64 WIRE 336 -16 336 -64 WIRE 336 144 240 144 WIRE 336 144 336 80 WIRE 336 432 320 432 WIRE 336 480 336 432 WIRE 336 640 240 640 WIRE 336 640 336 576 WIRE 352 -240 352 -256 WIRE 352 -64 336 -64 WIRE 352 -64 352 -96 WIRE 352 256 352 240 WIRE 352 432 336 432 WIRE 352 432 352 400 WIRE 384 -64 352 -64 WIRE 384 432 352 432 WIRE 432 -256 352 -256 WIRE 432 -144 432 -256 WIRE 432 144 336 144 WIRE 432 144 432 -48 WIRE 432 192 432 144 WIRE 432 240 352 240 WIRE 432 240 432 192 WIRE 432 352 432 240 WIRE 432 640 336 640 WIRE 432 640 432 448 WIRE 464 -256 432 -256 WIRE 464 192 432 192 WIRE 464 640 432 640 WIRE 480 192 464 192 WIRE 608 -256 464 -256 WIRE 608 -240 608 -256 WIRE 608 -144 608 -160 WIRE 608 -32 608 -48 WIRE 608 256 608 -32 WIRE 608 416 608 336 WIRE 608 432 608 416 WIRE 608 544 608 528 WIRE 608 640 464 640 WIRE 608 640 608 624 WIRE 656 -256 608 -256 WIRE 656 640 608 640 WIRE 688 -96 672 -96 WIRE 688 -32 608 -32 WIRE 688 -32 688 -96 WIRE 688 32 544 32 WIRE 688 48 688 32 WIRE 688 128 688 112 WIRE 688 192 560 192 WIRE 688 208 688 192 WIRE 688 304 688 272 WIRE 688 416 608 416 WIRE 688 480 672 480 WIRE 688 480 688 416 WIRE 704 -96 688 -96 WIRE 704 480 688 480 WIRE 768 -256 736 -256 WIRE 768 -240 768 -256 WIRE 768 -144 768 -160 WIRE 768 32 688 32 WIRE 768 32 768 -48 WIRE 768 432 768 32 WIRE 768 544 768 528 WIRE 768 640 736 640 WIRE 768 640 768 624 WIRE 848 -256 768 -256 WIRE 848 640 768 640 WIRE 880 112 848 112 WIRE 880 192 688 192 WIRE 880 192 880 112 WIRE 880 208 880 192 WIRE 880 304 880 288 WIRE 944 -256 928 -256 WIRE 944 640 928 640 FLAG 688 304 0 FLAG 880 304 0 FLAG 944 640 0 FLAG 944 -256 0 FLAG 464 -256 Vcc FLAG 464 640 Vee FLAG 112 240 Vb FLAG -1152 208 0 FLAG -688 -160 Vo IOPIN -688 -160 In FLAG 848 112 Vo IOPIN 848 112 Out FLAG -384 -192 0 FLAG 464 192 x FLAG 688 128 0 FLAG -1136 80 Vin IOPIN -1136 80 Out FLAG 80 32 ifb IOPIN 80 32 In FLAG -1136 0 0 FLAG -1008 -208 ifb IOPIN -1008 -208 In FLAG 544 32 ifb IOPIN 544 32 Out FLAG -192 160 0 FLAG -576 160 0 FLAG -848 240 0 FLAG -992 80 Vin IOPIN -992 80 In SYMBOL npn -336 480 R0 WINDOW 0 51 32 Left 0 WINDOW 3 51 64 Left 0 SYMATTR InstName Q6 SYMATTR Value 2N4401 SYMBOL npn -432 480 M0 WINDOW 0 51 32 Left 0 WINDOW 3 51 64 Left 0 SYMATTR InstName Q5 SYMATTR Value 2N4401 SYMBOL nmos 384 -144 R0 WINDOW 3 56 32 Left 0 WINDOW 0 57 64 Left 0 SYMATTR Value STP14NF12 SYMATTR InstName M2 SYMBOL pnp 272 80 M180 WINDOW 0 51 64 Left 0 WINDOW 3 51 32 Left 0 SYMATTR InstName Q8 SYMATTR Value 2N2907 SYMBOL diode 256 -48 R270 WINDOW 0 32 32 VTop 0 WINDOW 3 0 32 VBottom 0 SYMATTR InstName D6 SYMATTR Value 1N914 SYMBOL pnp 64 -96 M180 WINDOW 0 51 64 Left 0 WINDOW 3 51 32 Left 0 SYMATTR InstName Q7 SYMATTR Value 2N4403 SYMBOL res 256 144 R180 WINDOW 0 36 76 Left 0 WINDOW 3 36 40 Left 0 SYMATTR InstName R13 SYMATTR Value 220 SYMBOL voltage -64 480 R0 SYMATTR InstName V1 SYMATTR Value 12V SYMBOL cap 96 160 R270 WINDOW 0 32 32 VTop 0 WINDOW 3 0 32 VBottom 0 WINDOW 123 32 0 VLeft 0 SYMATTR InstName C4 SYMATTR Value 100µ SYMATTR Value2 IC=11V SYMBOL diode -80 224 M180 WINDOW 0 48 48 Left 0 WINDOW 3 48 24 Left 0 SYMATTR InstName D4 SYMATTR Value MURS120 SYMBOL voltage 944 640 R90 WINDOW 0 -32 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName V3 SYMATTR Value 45V SYMBOL voltage 832 -256 R270 WINDOW 0 32 56 VTop 0 WINDOW 3 -32 56 VBottom 0 SYMATTR InstName V2 SYMATTR Value 45V SYMBOL ind2 464 208 R270 WINDOW 0 32 56 VTop 0 WINDOW 3 5 56 VBottom 0 SYMATTR InstName L1 SYMATTR Value 30µ SYMATTR SpiceLine Rser=10m Rpar=10k SYMATTR Type ind SYMBOL cap 672 208 R0 SYMATTR InstName C8 SYMATTR Value 680n SYMBOL npn -288 352 M0 WINDOW 0 -32 32 Right 0 WINDOW 3 -32 64 Right 0 SYMATTR InstName Q4 SYMATTR Value 2N5550 SYMBOL npn -480 352 R0 WINDOW 0 -32 32 Right 0 WINDOW 3 -32 64 Right 0 SYMATTR InstName Q3 SYMATTR Value 2N5550 SYMBOL res -400 528 R0 SYMATTR InstName R9 SYMATTR Value 75 SYMBOL res 240 -80 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R12 SYMATTR Value 33 SYMBOL res 48 -144 R180 WINDOW 0 36 76 Left 0 WINDOW 3 36 40 Left 0 SYMATTR InstName R11 SYMATTR Value 150 SYMBOL schottky 112 -48 M270 WINDOW 0 32 32 VTop 0 WINDOW 3 -3 32 VBottom 0 SYMATTR InstName D5 SYMATTR Value BAT54 SYMATTR Description Diode SYMATTR Type diode SYMBOL nmos 384 352 R0 WINDOW 3 56 64 Left 0 SYMATTR Value STP14NF12 SYMATTR InstName M1 SYMBOL pnp 272 576 M180 WINDOW 0 51 64 Left 0 WINDOW 3 51 32 Left 0 SYMATTR InstName Q10 SYMATTR Value 2N2907 SYMBOL diode 256 448 R270 WINDOW 0 32 32 VTop 0 WINDOW 3 0 32 VBottom 0 SYMATTR InstName D8 SYMATTR Value 1N914 SYMBOL pnp 64 400 M180 WINDOW 0 51 64 Left 0 WINDOW 3 51 32 Left 0 SYMATTR InstName Q9 SYMATTR Value 2N4403 SYMBOL res 256 640 R180 WINDOW 0 36 76 Left 0 WINDOW 3 36 40 Left 0 SYMATTR InstName R17 SYMATTR Value 220 SYMBOL res 240 416 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R16 SYMATTR Value 33 SYMBOL res 48 352 R180 WINDOW 0 36 76 Left 0 WINDOW 3 36 40 Left 0 SYMATTR InstName R15 SYMATTR Value 150 SYMBOL pnp -560 80 M180 WINDOW 0 51 64 Left 0 WINDOW 3 51 32 Left 0 SYMATTR InstName Q1 SYMATTR Value 2N5401 SYMBOL pnp -208 80 R180 WINDOW 0 51 64 Left 0 WINDOW 3 51 32 Left 0 SYMATTR InstName Q2 SYMATTR Value 2N5401 SYMBOL diode -352 144 M270 WINDOW 0 32 32 VTop 0 WINDOW 3 0 32 VBottom 0 SYMATTR InstName D2 SYMATTR Value 1N914 SYMBOL diode -416 240 R270 WINDOW 0 32 32 VTop 0 WINDOW 3 0 32 VBottom 0 SYMATTR InstName D3 SYMATTR Value 1N914 SYMBOL current -384 -160 R0 WINDOW 0 48 16 Left 0 WINDOW 3 48 48 Left 0 SYMATTR InstName I1 SYMATTR Value 3m SYMBOL schottky 112 448 M270 WINDOW 0 32 32 VTop 0 WINDOW 3 -3 32 VBottom 0 SYMATTR InstName D7 SYMATTR Value BAT54 SYMATTR Description Diode SYMATTR Type diode SYMBOL voltage -1152 96 R0 WINDOW 0 53 70 Bottom 0 WINDOW 3 -16 183 Left 0 WINDOW 123 0 0 Left 0 WINDOW 39 60 56 VTop 0 SYMATTR InstName Vi SYMATTR Value PULSE({-a} {a} 0 1u 1u 49u 100u) SYMBOL pnp 672 -48 R180 WINDOW 0 51 64 Left 0 WINDOW 3 51 32 Left 0 SYMATTR InstName Q11 SYMATTR Value 2N5401 SYMBOL npn 672 432 M0 WINDOW 0 51 32 Left 0 WINDOW 3 51 64 Left 0 SYMATTR InstName Q13 SYMATTR Value 2N5550 SYMBOL res 624 -144 R180 WINDOW 0 36 76 Left 0 WINDOW 3 36 40 Left 0 SYMATTR InstName R20 SYMATTR Value 100 SYMBOL res 624 640 R180 WINDOW 0 36 76 Left 0 WINDOW 3 36 40 Left 0 SYMATTR InstName R23 SYMATTR Value 100 SYMBOL pnp 704 -48 M180 WINDOW 0 51 64 Left 0 WINDOW 3 51 32 Left 0 SYMATTR InstName Q12 SYMATTR Value 2N5401 SYMBOL npn 704 432 R0 WINDOW 0 51 32 Left 0 WINDOW 3 51 64 Left 0 SYMATTR InstName Q14 SYMATTR Value 2N5550 SYMBOL res 752 -256 R0 SYMATTR InstName R22 SYMATTR Value 100 SYMBOL res 752 528 R0 SYMATTR InstName R25 SYMATTR Value 100 SYMBOL res 752 -272 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R21 SYMATTR Value 50m SYMBOL res 752 624 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R24 SYMATTR Value 50m SYMBOL res 624 352 R180 WINDOW 0 36 76 Left 0 WINDOW 3 36 40 Left 0 SYMATTR InstName R19 SYMATTR Value 10k SYMBOL cap 672 112 M180 WINDOW 0 24 64 Left 0 WINDOW 3 24 8 Left 0 SYMATTR InstName C7 SYMATTR Value 150p SYMBOL res 368 -80 R180 WINDOW 0 36 76 Left 0 WINDOW 3 36 40 Left 0 SYMATTR InstName R14 SYMATTR Value 10 SYMBOL cap 368 -240 M0 WINDOW 0 32 16 Left 0 WINDOW 3 32 48 Left 0 SYMATTR InstName C5 SYMATTR Value 22p SYMBOL res 368 416 R180 WINDOW 0 36 76 Left 0 WINDOW 3 36 40 Left 0 SYMATTR InstName R18 SYMATTR Value 10 SYMBOL cap 368 256 M0 WINDOW 0 32 16 Left 0 WINDOW 3 32 48 Left 0 SYMATTR InstName C6 SYMATTR Value 22p SYMBOL res 64 16 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R10 SYMATTR Value 3k3 SYMBOL res -592 16 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R8 SYMATTR Value 3k3 SYMBOL res -1024 -224 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R1 SYMATTR Value 1k SYMBOL Miscxvaristor -848 112 M90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName D1 SYMATTR Value limit SYMATTR Prefix D SYMBOL res -736 16 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R7 SYMATTR Value 3k3 SYMBOL cap -848 -144 M0 WINDOW 3 32 48 Left 0 WINDOW 0 32 16 Left 0 SYMATTR Value 100p SYMATTR InstName C1 SYMBOL res -880 64 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R4 SYMATTR Value 4k3 SYMBOL res -848 -144 R270 WINDOW 0 32 56 VTop 0 WINDOW 3 0 56 VBottom 0 SYMATTR InstName R5 SYMATTR Value 1k5 SYMBOL res -736 -80 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R6 SYMATTR Value 28k7 SYMBOL res -1024 -128 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R2 SYMATTR Value 1k SYMBOL res -880 -32 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R3 SYMATTR Value 3k3 SYMBOL cap -208 64 R0 SYMATTR InstName C3 SYMATTR Value 47p SYMBOL cap -560 64 M0 SYMATTR InstName C2 SYMATTR Value 47p SYMBOL Opampsopamp -1088 -80 R0 WINDOW 3 0 96 Left 0 SYMATTR InstName U1 SYMATTR SpiceLine "" SYMATTR SpiceLine2 "" SYMBOL Opampsopamp -800 160 R0 WINDOW 3 0 96 Left 0 SYMATTR InstName U2 SYMATTR SpiceLine "" SYMATTR SpiceLine2 "" SYMBOL res 864 192 R0 SYMATTR InstName Ro SYMATTR Value {Ro} TEXT -1168 688 Left 0 !.tran 0 225u 25u uic TEXT -120 672 Left 0 !.model STP14NF12 vdmos (Rg=5 Rd=90m Rs=70m Vto=3.5 Kp=3n+ Cgdmax=200p Cgdmin=20p Cgs=420p Cjo=60p Is=10p Rb=140m) TEXT -1168 312 Left 0 !.model limit d(Ron=1u Vfwd=5 Vrev=5) TEXT -1168 352 Left 0 !.subckt opamp 1 2 3nG1 0 3 2 1 10knC1 3 0 160µ Rpar=100nD1 3 0 limn.model lim d(Ron=1u Vfwd=12 Vrev=12)n.ends opamp TEXT -1168 648 Left 0 !.step param Ro list 1G 6 1u TEXT -1168 624 Left 0 !.param a=5 Ro=6 TEXT -384 -312 Center 0 ;UcD180 Class D Amplifier Power Stage ndriven by LeapFrog controlnby analogspiceman, March, 2005 TEXT -1168 528 Left 0 ;10kHz square wave response intonopen, nominal, and short circuits.nPlot V(o) and I(L1)

analog wrote:

[cut first example]

Here's an example of a self oscillating class d amplifier based on the UcD180 design that contains the output filter within its feedback loop (provides no inherent output current limiting):

This and the previously posted schematic are detailed simulation files for full bandwidth 180W class-d amplifiers. The UcD is available for do-it-yourselfers at low cost from

and seems to be a fine product.

For more information see their web site or read about it and other home brew projects on the do-it-yourselfer's audio forum at

under the Class D section. (Note: I have no commercial affiliation with either of these two entities - I just am fascinated with class-d amplifier design.)

The two simulation files look at amplifier response into a 10kHz square wave at open, nominal and short circuits. Both amplifiers perform similarly at full load, but at open and short circuits...

Well, I'll leave it for you to be the judge. :)

Regards -- analog(spiceman)

~~~~ ClassD_UcD180.asc (cut&paste & mind the word wrap) ~~~~ Version 4 SHEET 1 1328 1060 WIRE -896 128 -896 96 WIRE -896 224 -896 208 WIRE -880 96 -896 96 WIRE -864 96 -880 96 WIRE -752 -144 -752 -160 WIRE -752 -64 -752 -80 WIRE -752 48 -752 16 WIRE -752 96 -784 96 WIRE -752 96 -752 48 WIRE -752 112 -752 96 WIRE -752 224 -752 176 WIRE -720 48 -752 48 WIRE -656 0 -656 -32 WIRE -656 128 -656 96 WIRE -656 224 -656 128 WIRE -656 400 -656 224 WIRE -656 480 -656 400 WIRE -656 640 -656 576 WIRE -640 400 -656 400 WIRE -576 128 -656 128 WIRE -576 224 -656 224 WIRE -576 352 -576 320 WIRE -576 528 -592 528 WIRE -576 528 -576 448 WIRE -544 -144 -544 -160 WIRE -544 -32 -656 -32 WIRE -544 -32 -544 -64 WIRE -544 528 -576 528 WIRE -544 544 -544 528 WIRE -544 640 -656 640 WIRE -544 640 -544 624 WIRE -512 352 -512 288 WIRE -512 528 -544 528 WIRE -512 528 -512 448 WIRE -496 528 -512 528 WIRE -432 -32 -544 -32 WIRE -432 0 -432 -32 WIRE -432 128 -512 128 WIRE -432 128 -432 96 WIRE -432 224 -512 224 WIRE -432 224 -432 128 WIRE -432 400 -448 400 WIRE -432 400 -432 224 WIRE -432 480 -432 400 WIRE -432 640 -544 640 WIRE -432 640 -432 576 WIRE -336 -64 -336 -112 WIRE -336 48 -368 48 WIRE -336 48 -336 16 WIRE -336 96 -336 48 WIRE -336 112 -336 96 WIRE -336 224 -336 192 WIRE -240 -112 -336 -112 WIRE -240 -96 -240 -112 WIRE -240 -16 -240 -32 WIRE -240 96 -336 96 WIRE -240 96 -240 64 WIRE -240 112 -240 96 WIRE -240 224 -240 176 WIRE -176 -112 -240 -112 WIRE -128 288 -512 288 WIRE -128 288 -128 -64 WIRE -128 320 -576 320 WIRE -128 432 -128 320 WIRE -64 144 -64 -256 WIRE -64 160 -64 144 WIRE -64 240 -64 224 WIRE -64 496 -64 240 WIRE -64 640 -432 640 WIRE -64 640 -64 576 WIRE 32 -256 -64 -256 WIRE 32 -240 32 -256 WIRE 32 -144 32 -160 WIRE 32 -64 -128 -64 WIRE 32 -64 32 -144 WIRE 32 240 -64 240 WIRE 32 256 32 240 WIRE 32 352 32 336 WIRE 32 432 -128 432 WIRE 32 432 32 352 WIRE 48 -64 32 -64 WIRE 48 432 32 432 WIRE 64 -144 32 -144 WIRE 64 352 32 352 WIRE 96 144 -64 144 WIRE 112 240 32 240 WIRE 128 -256 32 -256 WIRE 128 -192 128 -256 WIRE 128 -64 112 -64 WIRE 128 -64 128 -96 WIRE 128 240 112 240 WIRE 128 304 128 240 WIRE 128 432 112 432 WIRE 128 432 128 400 WIRE 144 -64 128 -64 WIRE 144 432 128 432 WIRE 240 -64 224 -64 WIRE 240 32 240 -64 WIRE 240 48 240 32 WIRE 240 144 160 144 WIRE 240 144 240 128 WIRE 240 432 224 432 WIRE 240 528 240 432 WIRE 240 544 240 528 WIRE 240 640 -64 640 WIRE 240 640 240 624 WIRE 256 -64 240 -64 WIRE 256 432 240 432 WIRE 272 32 240 32 WIRE 272 528 240 528 WIRE 336 -64 320 -64 WIRE 336 -16 336 -64 WIRE 336 144 240 144 WIRE 336 144 336 80 WIRE 336 432 320 432 WIRE 336 480 336 432 WIRE 336 640 240 640 WIRE 336 640 336 576 WIRE 384 -64 336 -64 WIRE 384 432 336 432 WIRE 432 -144 432 -256 WIRE 432 144 336 144 WIRE 432 144 432 -48 WIRE 432 192 432 144 WIRE 432 352 432 192 WIRE 432 640 336 640 WIRE 432 640 432 448 WIRE 464 -256 432 -256 WIRE 464 192 432 192 WIRE 464 640 432 640 WIRE 496 -256 464 -256 WIRE 496 192 464 192 WIRE 496 640 464 640 WIRE 592 -256 576 -256 WIRE 592 640 576 640 WIRE 608 192 576 192 WIRE 608 208 608 192 WIRE 608 304 608 272 WIRE 656 192 608 192 WIRE 720 -112 672 -112 WIRE 720 192 656 192 WIRE 720 192 720 -112 WIRE 720 208 720 192 WIRE 720 304 720 288 FLAG 608 304 0 FLAG 720 304 0 FLAG 592 640 0 FLAG 592 -256 0 FLAG 464 -256 Vcc FLAG 464 640 Vee FLAG 112 240 Vb FLAG -896 224 0 FLAG -336 224 0 FLAG -176 -112 o IOPIN -176 -112 In FLAG 672 -112 o IOPIN 672 -112 Out FLAG -544 -160 0 FLAG -240 224 0 FLAG 464 192 x FLAG -752 224 0 FLAG -752 -160 0 FLAG -880 96 i FLAG 656 192 o SYMBOL npn -496 480 R0 SYMATTR InstName Q6 SYMATTR Value 2N4401 SYMBOL npn -592 480 M0 SYMATTR InstName Q5 SYMATTR Value 2N4401 SYMBOL pnp 272 80 M180 WINDOW 0 48 64 Left 0 WINDOW 3 48 32 Left 0 SYMATTR InstName Q8 SYMATTR Value 2N2907 SYMBOL diode 256 -48 R270 WINDOW 0 32 32 VTop 0 WINDOW 3 0 32 VBottom 0 SYMATTR InstName D5 SYMATTR Value 1N914 SYMBOL pnp 64 -96 M180 WINDOW 0 48 64 Left 0 WINDOW 3 48 32 Left 0 SYMATTR InstName Q7 SYMATTR Value 2N4403 SYMBOL res 256 144 R180 WINDOW 0 36 76 Left 0 WINDOW 3 36 40 Left 0 SYMATTR InstName R9 SYMATTR Value 220 SYMBOL voltage -64 480 R0 SYMATTR InstName V1 SYMATTR Value 12V SYMBOL cap 96 160 R270 WINDOW 0 32 32 VTop 0 WINDOW 3 0 32 VBottom 0 WINDOW 123 32 0 VLeft 0 SYMATTR InstName C5 SYMATTR Value 100µ SYMATTR Value2 IC=11V SYMBOL diode -80 224 M180 WINDOW 0 48 48 Left 0 WINDOW 3 48 24 Left 0 SYMATTR InstName D3 SYMATTR Value MURS120 SYMBOL voltage 592 640 R90 WINDOW 0 -32 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName V3 SYMATTR Value 45V SYMBOL voltage 480 -256 R270 WINDOW 0 32 56 VTop 0 WINDOW 3 -32 56 VBottom 0 SYMATTR InstName V2 SYMATTR Value 45V SYMBOL ind 480 208 R270 WINDOW 0 32 56 VTop 0 WINDOW 3 5 56 VBottom 0 SYMATTR InstName L1 SYMATTR Value 30µ SYMATTR SpiceLine Rser=10m Rpar=10k SYMBOL cap 592 208 R0 SYMATTR InstName C6 SYMATTR Value 680n SYMBOL res 704 192 R0 SYMATTR InstName Ro SYMATTR Value {Ro} SYMBOL npn -448 352 M0 WINDOW 0 -32 32 Right 0 WINDOW 3 -32 64 Right 0 SYMATTR InstName Q4 SYMATTR Value 2N5550 SYMBOL npn -640 352 R0 WINDOW 0 -32 32 Right 0 WINDOW 3 -32 64 Right 0 SYMATTR InstName Q3 SYMATTR Value 2N5550 SYMBOL res -560 528 R0 SYMATTR InstName R6 SYMATTR Value 75 SYMBOL res -352 96 R0 SYMATTR InstName R4 SYMATTR Value 1k8 SYMBOL res -352 -80 R0 SYMATTR InstName R3 SYMATTR Value 8k2 SYMBOL res -256 -32 R0 SYMATTR InstName R5 SYMATTR Value 1k0 SYMBOL res 240 -80 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R8 SYMATTR Value 33 SYMBOL res 48 -144 R180 WINDOW 0 36 76 Left 0 WINDOW 3 36 40 Left 0 SYMATTR InstName R7 SYMATTR Value 150 SYMBOL schottky 112 -48 M270 WINDOW 0 32 32 VTop 0 WINDOW 3 0 32 VBottom 0 SYMATTR InstName D4 SYMATTR Value BAT54 SYMATTR Description Diode SYMATTR Type diode SYMBOL nmos 384 -144 R0 SYMATTR InstName M1 SYMATTR Value STP14NF12 SYMBOL pnp 272 576 M180 WINDOW 0 48 64 Left 0 WINDOW 3 48 32 Left 0 SYMATTR InstName Q10 SYMATTR Value 2N2907 SYMBOL diode 256 448 R270 WINDOW 0 32 32 VTop 0 WINDOW 3 0 32 VBottom 0 SYMATTR InstName D7 SYMATTR Value 1N914 SYMBOL pnp 64 400 M180 WINDOW 0 48 64 Left 0 WINDOW 3 48 32 Left 0 SYMATTR InstName Q9 SYMATTR Value 2N4403 SYMBOL res 256 640 R180 WINDOW 0 36 76 Left 0 WINDOW 3 36 40 Left 0 SYMATTR InstName R12 SYMATTR Value 220 SYMBOL res 240 416 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R11 SYMATTR Value 33 SYMBOL res 48 352 R180 WINDOW 0 36 76 Left 0 WINDOW 3 36 40 Left 0 SYMATTR InstName R10 SYMATTR Value 150 SYMBOL pnp -720 96 M180 WINDOW 0 48 64 Left 0 WINDOW 3 48 32 Left 0 SYMATTR InstName Q1 SYMATTR Value 2N5401 SYMBOL pnp -368 96 R180 WINDOW 0 48 64 Left 0 WINDOW 3 48 32 Left 0 SYMATTR InstName Q2 SYMATTR Value 2N5401 SYMBOL diode -512 144 M270 WINDOW 0 32 32 VTop 0 WINDOW 3 0 32 VBottom 0 SYMATTR InstName D1 SYMATTR Value 1N914 SYMBOL diode -576 240 R270 WINDOW 0 32 32 VTop 0 WINDOW 3 0 32 VBottom 0 SYMATTR InstName D2 SYMATTR Value 1N914 SYMBOL current -544 -144 R0 WINDOW 0 48 16 Left 0 WINDOW 3 48 48 Left 0 SYMATTR InstName I1 SYMATTR Value 3m SYMBOL schottky 112 448 M270 WINDOW 0 32 32 VTop 0 WINDOW 3 0 32 VBottom 0 SYMATTR InstName D6 SYMATTR Value BAT54 SYMATTR Description Diode SYMATTR Type diode SYMBOL voltage -896 112 R0 WINDOW 0 53 70 Bottom 0 WINDOW 3 32 144 Top 0 WINDOW 123 0 0 Left 0 WINDOW 39 60 56 VTop 0 SYMATTR InstName Vi SYMATTR Value PULSE(-5.95 5.95 1u 1u 1u 49u 100u) SYMBOL cap -256 -96 R0 SYMATTR InstName C4 SYMATTR Value 150p SYMBOL cap -256 112 R0 SYMATTR InstName C3 SYMATTR Value 33p SYMBOL res -768 80 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R1 SYMATTR Value 1k5 SYMBOL res -736 32 R180 WINDOW 0 36 76 Left 0 WINDOW 3 36 40 Left 0 SYMATTR InstName R2 SYMATTR Value 1k0 SYMBOL cap -768 -144 R0 SYMATTR InstName C2 SYMATTR Value 150p SYMBOL cap -768 112 R0 SYMATTR InstName C1 SYMATTR Value 33p SYMBOL nmos 384 352 R0 SYMATTR InstName M2 SYMATTR Value STP14NF12 TEXT -1056 616 Left 0 !.tran 0 275u 75u uic TEXT -256 688 Left 0 !.model STP14NF12 vdmos (Rg=5 Rd=90m Rs=70m Vto=3.5 Kp=3n+ Cgdmax=200p Cgdmin=20p Cgs=420p Cjo=60p Is=10p Rb=140m) TEXT -304 584 Left 0 ;Io 7Arms 10Ap TEXT -304 520 Left 0 ;65dB PSRR TEXT -304 552 Left 0 ;93 % efficiency TEXT -392 -256 Center 0 ;UcD180 Class D Amplifier Schematic nmy guesstimate by analogspicemannMarch, 2005 TEXT -304 488 Left 0 ;Fosc 415kHz TEXT -1056 584 Left 0 !.step param Ro list 1G 6 1u TEXT -1056 480 Left 0 ;10kHz square wave response intonopen, nominal, and short circuits.nPlot V(o) and I(L1)

Thanks, analog.

I will have to process all this in time.

Good day!

--
_______________________________________________________________________
Christopher R. Carlen
Principal Laser/Optical Technologist
Sandia National Laboratories CA USA
crcarleRemoveThis@BOGUSsandia.gov
NOTE, delete texts: "RemoveThis" and "BOGUS" from email address to reply.

"Chris Carlen" wrote in message news: snipped-for-privacy@news4.newsguy.com...

The LTSpice simulation I posted Sunday, with suitable corrections for some posting anomalies, can be used to show how the poles move versus loop gain and see the range of loop responses available.

Below, (after posting, I hope), is a revised form of the same controller with a pair of solutions selected by NS. (Loop gain GX, LPF scaling LPFS, and scaling of the zero pair and realization pole, ZW, are all set by NS.) I've set it up so that the controller response can also be scaled (approximately, ignoring op-amp poles), not just the LC LPF. This makes it more convenient to simulate for the output filter you may want to actually build. As you can see, it is quite possible to move the LPF poles closer to the origin as I have suggested.

The group delay is (about) either 33uS or 50uS and flat within a few hundred nS out to 400 Hz. You might note that, after shifting by the controller, the response is close to what your bare LC LPF was doing.

========== begin lcyanka.asc ============= Version 4 SHEET 1 880 740 WIRE -528 496 -528 448 WIRE -512 240 -512 224 WIRE -512 336 -512 320 WIRE -496 448 -528 448 WIRE -496 528 -496 448 WIRE -480 448 -496 448 WIRE -480 528 -496 528 WIRE -432 224 -512 224 WIRE -368 224 -432 224 WIRE -368 448 -400 448 WIRE -368 528 -400 528 WIRE -352 448 -368 448 WIRE -352 528 -368 528 WIRE -256 224 -288 224 WIRE -256 320 -256 224 WIRE -256 400 -256 352 WIRE -256 496 -256 480 WIRE -240 320 -256 320 WIRE -240 352 -256 352 WIRE -224 224 -256 224 WIRE -144 224 -160 224 WIRE -144 336 -176 336 WIRE -144 336 -144 224 WIRE -128 496 -256 496 WIRE -128 496 -128 384 WIRE -96 336 -144 336 WIRE -80 336 -96 336 WIRE -80 384 -128 384 WIRE -64 496 -128 496 WIRE -32 208 -32 192 WIRE -32 304 -32 288 WIRE 16 192 -32 192 WIRE 16 384 0 384 WIRE 16 480 0 480 WIRE 16 480 16 384 WIRE 32 512 0 512 WIRE 32 544 32 512 WIRE 48 192 16 192 WIRE 48 544 32 544 WIRE 64 384 16 384 WIRE 80 480 16 480 WIRE 144 544 128 544 WIRE 144 560 144 544 WIRE 160 192 128 192 WIRE 160 224 160 192 WIRE 160 304 160 288 WIRE 192 192 160 192 WIRE 208 192 192 192 WIRE 208 384 144 384 WIRE 208 384 208 192 WIRE 208 416 208 384 WIRE 208 480 160 480 WIRE 256 192 208 192 WIRE 256 208 256 192 WIRE 256 304 256 288 WIRE 256 400 256 384 FLAG -512 336 0 FLAG -32 304 0 FLAG 256 400 0 FLAG 160 304 0 FLAG -528 496 0 FLAG -368 448 VP FLAG -208 304 VP FLAG -32 464 VP FLAG -368 528 VN FLAG -32 528 VN FLAG -208 368 VN FLAG -432 224 VS FLAG 192 192 VX FLAG 16 192 VA FLAG -96 336 VC FLAG 144 560 0 SYMBOL res 240 288 R0 SYMATTR InstName R1 SYMATTR Value 2.5 SYMBOL ind 240 192 R0 SYMATTR InstName L1 SYMATTR Value 0m25 SYMBOL cap 144 224 R0 WINDOW 0 -8 29 Right 0 WINDOW 3 5 59 Right 0 SYMATTR InstName C1 SYMATTR Value {7u2/LPFS} SYMBOL ind 32 208 R270 WINDOW 0 32 56 VTop 0 WINDOW 3 4 45 VBottom 0 SYMATTR InstName L2 SYMATTR Value {22u5/LPFS} SYMBOL bv -32 192 R0 WINDOW 0 -28 19 Right 0 WINDOW 3 362 -57 Right 0 SYMATTR InstName B1 SYMATTR Value V={if(abs(GX*V(VC))>30, 30*sgn(V(VC)), GX*V(VC))} SYMBOL voltage -512 224 R0 WINDOW 3 -56 151 Left 0 WINDOW 123 21 95 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V1 SYMATTR Value PWL(0 0 1m 0 1.01m 1 2m 1) SYMATTR Value2 AC 1 SYMBOL voltage -384 448 R90 WINDOW 0 -14 103 VBottom 0 WINDOW 3 4 10 VTop 0 SYMATTR InstName V2 SYMATTR Value 10 SYMBOL voltage -496 528 R270 WINDOW 0 -32 10 VTop 0 WINDOW 3 -4 100 VBottom 0 SYMATTR InstName V3 SYMATTR Value 10 SYMBOL cap 224 480 R180 WINDOW 0 -7 37 Right 0 WINDOW 3 -6 9 Right 0 SYMATTR InstName C2 SYMATTR Value 1n SYMBOL res 160 368 R90 WINDOW 0 -5 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R3 SYMATTR Value {rz} SYMBOL res 16 368 R90 WINDOW 0 -6 49 VBottom 0 WINDOW 3 33 90 VTop 0 SYMATTR InstName R4 SYMATTR Value {rz} SYMBOL cap -160 240 M270 WINDOW 0 23 7 VTop 0 WINDOW 3 0 32 VBottom 0 SYMATTR InstName C3 SYMATTR Value 1n SYMBOL res -384 208 M90 WINDOW 0 -3 73 VBottom 0 WINDOW 3 35 63 VTop 0 SYMATTR InstName R5 SYMATTR Value {rz} SYMBOL res 176 464 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 34 8 VTop 0 SYMATTR InstName R2 SYMATTR Value {rz/pzr} SYMBOL res -240 384 M0 WINDOW 0 39 51 Left 0 WINDOW 3 31 90 Left 0 SYMATTR InstName R6 SYMATTR Value {rz} SYMBOL res 144 528 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R7 SYMATTR Value {rz/2} SYMBOL Opamps\\\\LT1215 -32 432 M0 SYMATTR InstName U1 SYMBOL Opamps\\\\LT1215 -208 272 R0 SYMATTR InstName U2 TEXT -204 606 Left 0 !.tran 0 2m 0 1u TEXT -496 40 Left 0 !.param GX={table(NS,1,125,2,75)} TEXT -496 72 Left 0 !.param LPFS={table(NS,1,0.1,2,0.25)} TEXT -496 104 Left 0 !.param ZW={table(NS,1,40k,2,60k)}, pzr=10 TEXT -104 8 Left 0 ;For LPFS=1, L2.C2 poles at +/- j * 78.6K r/S TEXT -496 160 Left 0 !.param rz={1/(1n*ZW)} TEXT -496 8 Left 0 !.step param NS list 1 2 TEXT -288 -40 Left 0 ;Control of Single-Stage LC LPF ========== end lcyanka.asc =============

There are a number of steps remaining between the above and a real circuit. The scaling between the controller and the PWM does not reflect your 80V output range. There should be some careful attention given to limiting behavior because the loop is not stable for a range of lower loop gain values. (The LC poles move into the RHP and back into the LHP as loop gain is increased from 0.) This means that limiting in an unfortunate location could serve to reduce the loop gain and permit what is known as a limit cycle oscillation. It may also be necessary to introduce some additional low pass filtering to keep the chop frequency from appearing too much at the output of the controller.

--
--Larry Brasfield
email: donotspam_larry_brasfield@hotmail.com
Above views may belong only to me.

Yes, tight DC performance is needed. Gain can vary a few % but offset not.

There are also nonlinearities in the transfer of the SA60 that should be servoed out. Thus, an integrator is desired.

I don't want to use a gapped core since they don't work well with the physical constraints. I want a low profile off the PCB. I am choosing to use a Magnetics Inc. Kool-mu toroid core. I originally calculated for 100kHz switching freq., 10kHz LPF cutoff, so 27uH. Bumping the inductance down a little bit should make the same cores actually hold better than the original 75% of inductance at 10A. Haven't done the math again yet, but hopefully about 80%.

But that doesn't help much. A pair of 225uH inductors + 2x72uF of caps that can handle 10A is likely to be larger than my equalizer and may very well dissipate a lot of power anyway. Maybe the equalizer isn't so bad. Remember, for the real application, there really will be almost no frequency content above 150Hz. The extended bandwidth is just for phase flatness at the low end.

loop, so this is virgin territory.

[edit]

Ok, other than the question marks to which Genome unsurprisingly overreacted, I can use the simulation.

Thanks for the demo. I think I can learn to compensate in this manner. For now, it seems to my advantage to procede with the simple but functional circuit that I'm using. But your input has provided material for further investigation.

The smart thing to do would be to make the PCB design flexible enough to implement several compensation approaches. I'm already planning to make it switchable to become a current source. That would ultimately make more sense for a position servo. But for now I'm in voltage drive due to legacy issues.

Thanks for the input.

Good day!

--
_______________________________________________________________________
Christopher R. Carlen
Principal Laser/Optical Technologist
Sandia National Laboratories CA USA
crcarleRemoveThis@BOGUSsandia.gov
NOTE, delete texts: "RemoveThis" and "BOGUS" from email address to reply.

I'm not bothering with the filter at all. My filter is reasonable, at

22.5uH and 7.2uH. Larry proposed making the values 10x larger in order to demonstrate his post-filter compensation idea.

But that doesn't seem attractive to me since the gain of eliminating the equalizer (just to be clear, the "equalizer" is the series RC across the load RL to cancel out most of the reactance of the L) is offset by unrealistic LC filter values.

It is also true that the load inductance is likely to be non-linear due to the fact that it is a PM linear motor. I don't expect perfect performance from the filter. Nor should it be a problem because any of the wigglies in the overall response are at much higher frequencies than the application involves. The only time they will become relevant is in other potential applications where the bandwidth approaches the limits of the amp.

Yes.

Are you saying that you would incline toward overdamping the output filter so that it's response is not so sensitive to load reactance, and just accepting the increased ripple that would result?

Or perhaps rather, putting the output filter cutoff at a much higher frequency than the amp's bandwidth so that any peaking or drooping caused by load reactance is out of band anyway?

Good day!

--
_______________________________________________________________________
Christopher R. Carlen
Principal Laser/Optical Technologist
Sandia National Laboratories CA USA
crcarleRemoveThis@BOGUSsandia.gov
NOTE, delete texts: "RemoveThis" and "BOGUS" from email address to reply.

The controller I posted has an integrator enforcing output accuracy. This will take out variation due to that DC resistance, leaving only an efficiency issue.

I took the LPF down to 1/10 the initial frequency to show that, after the effects of pole shifting by the controller, the OP's delay requirement would still be easily met. In my post this morning, there was also a solution with the LPF set at 1/4 the initial frequency. It is also possible to compensate the loop with the filter at the initial 22.5uH and 7.2uF, but the loop bandwith ends up being a bit excessive and, with the 80 Vpp chopped input, the ripple is near 1 Vpp. I thought that was a little much given the application, but certainly must defer to the OP's judgement on that.

Seems reasonable, as long as other problems do not drive one to use other criteria.

I did.

I'm not sure what your point is. I think everbody understands that an output filter is needed. And most people looking at how an H bridge works would appreciate that some high frequency, spikey common mode noise will need to be filtered off.

--
--Larry Brasfield
email: donotspam_larry_brasfield@hotmail.com
Above views may belong only to me.

Then you should use the smallest possible inductors because of the DC resistance.

Then why bother with the filter so much? Any filter will suffer from non-linearities in the filter components and the load (especially the filter components you describe) at these power levels. Also, I suspect the load will not be a constant inductor which adds extra non-linearities as well which in turn will affect the filter.

Besides, 225uH inductors and 72uF capacitors sound way too large to me. I expect the inductors 10uH to 47uH and the capacitors from 1uF to

10uF.

I think it's better to size the inductors and capacitors according to the amount of energy they should store and the amount of ripple you tolerate like in a switching power supply. Did you already read my answer to John Woodgate?

"In other words, butterworth, bessel and zobel look nice in theory, but their practical use is very limited when it comes to class D amplifiers.

I found out that using some inductors and capacitors to smear the pulses into something that looks like a signal and using a common mode filter as a final stage to get rid of the HF components works much better."

--
Reply to nico@nctdevpuntnl (punt=.)
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I suppose there is an outer loop which controls the speed/position of the servo you are controlling through the class-D amplifier. I assume this outer loop should flatten the closed loop frequency response of the entire control system. I think it is easier to achieve closed loop stability by placing limits on the amplifiers input (bandwidth / gain) than at its output.

I'm saying: treat the output like it is a switching PSU with a synchronous rectifier and build the filter around a worst case scenario (maximum current and allowable ripple). Then you know the worst case signal from the output for whatever load is attached. Using that knowledge you can choose whether further filtering is required or not, but this choice is probably based on EMI requirements and sensitivity to HF ripple of the load.

--
Reply to nico@nctdevpuntnl (punt=.)
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