Re: PCB trace spacing for voltage levels

Example TO-220 leadform options:

Best regards, Spehro Pefhany

--
"it\'s the network..."                          "The Journey is the reward"
speff@interlog.com             Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog  Info for designers:  http://www.speff.com

Thanks!

cheers, Jamie

I modified the fets to use option 107 in that pdf. The PCB now can have

0.1" trace spacing to the fet pads, but the TO-220 pins are still closer together near the bottom of the plastic package. So if anything shorts from high voltage it will be the pins shorting together. I don't know if this is acceptable for UL and/or safer than the PCB traces shorting?

cheers, Jamie

The normal procedure for evaluating creepage that is less than stipulated by a standard, in a non-isolation function, is to apply single fault abnormal shorts in that location, while monitoring safety-critical features.

This is intended to demonstrate that the failure mode does not result in a hazardous condition - tracks do not open, material does not get ejected from the package and an external wrap of 'cheese cloth' is not ignited. The resulting mess is then hipotted.

Obviously, substandard spacing cannot be permitted before the first fusible link location in the primary circuit. Downstream locations have to be examined individually.

Power semiconductors, whether they meet spacing requirements or not, will be subjected to the single-fault abnormal testing as a matter of course, simply to evaluate the assembly's integrity under common fault conditions.

Substandard spacings between hazardous and ELV or SELV circuits or the safety ground hardware isn't permitted under any circumstances.

RL