Q to Win re:oscillation in high-voltage MOSFETS

I have tried the models for the FQD2N100TM FET and have some questions.

1) The log(Is) vs Vgs relationship does not hold below about 1mA, and i need that to work to at least 1uA; preferably to 10nA. 2) I see nonlinear *gate current*: 10uA at 0V, 0uA at 50V with "knees" near 5V and 9V. I had the mistaken impression that gates were insulated from the channel, and that there were no batteries inside FETs. 3) Could you please provide a resistive SPICE single-FET circuit that might oscillate?

Actually, *both* suck. Try a resistor from Vgs sweep to gate, another resistor from drain to fixed Vdss. Start with low values and play mostly with the gate resistor.

I'm sorry, your point was?

--
 Thanks,
    - Win

Using LTspice, i get an error message: Fatal Error: Too many parameters for subcircuit type "fqd2n100" (instance: xm1) TopSpice does not complain, and the following shows a problem: Test Fet (TF.CIR) .OPTIONS ACCT LIST NODE OPTS .TEMP 27 ;90 .DC Vg 4.50 5.00 0.001 Rin 91 01 1E6 ;Vg VS Is Looks good if low value Rdo 92 02 1E-3 Vd 92 00 100V Vg 91 00 4.7V

• D G S X1 02 01 03 FQD2N100 Rs 03 04 1E-3 V2 00 04 0V ;MEASURE Is .PRINT I(Rs) .PLOT I(Rs) .SAVE

.SUBCKT FQD2N100 d g s ;Note mod on designations - no help Rg g 1 0.04 M1 2 1 3 3 DMOS L=1u W=1u .MODEL DMOS NMOS(VTO=4.66 KP=1.9 LEVEL=3) Cgs 1 3 380p Rd d 4 3.5 Dds 3 4 DDS .MODEL DDS D(BV=1050 M=0.42 CJO=35p VJ=0.12) Dbody 3 d DBODY .MODEL DBODY D(IS=2.8E-13 N=1.00 RS=0.005 EG=1.10 TT=520n) Ra 4 2 3.5 Rs 3 5 0.024 Ls 5 s 2.6n M2 1 8 6 6 INTER E2 8 6 4 1 2 .MODEL INTER NMOS(VTO=0 KP=10 LEVEL=1) CGDMAX 7 4 380p RCGD 7 4 1E7 DGD 6 4 DGD RDGD 4 6 1E7 .MODEL DGD D(M=0.52 CJO=380p VJ=0.12) M3 7 9 1 1 INTER E3 9 1 4 1 -2 .ENDS

.END

This "model" appears to work with low gate resistance values, but if large, the result is very wrong and shows gate current that should not exist. And it might be troubling that LTspice barfs on it. Both point to one or more problems in the model.

The portion of the model I modified works fine. IIUC, you're complaining about the FET's dynamic capacitance models. This is one of the standard Motorola power mosfet Spice models (see Motorola's AN1043, pub 1989), adopted by Fairchild and others, so I'd think LTSpice should certainly be able to handle it.

MOSFET capacitances change dramatically (up to a factor 10x) in the region of 5 to 12V, and modeling this has always been difficult. Many models use voltage-controlled switches, which can give Spice serious trouble (e.g., see Fairchild app 7533). The Motorola approach turns on two small "INTER" FETs instead, which should be better for Spice convergence, etc. There is another approach I like, pioneered at RCA by Frank Wheatley and others, which involves adding a cascode JFET to the drain (see Fairchild app AN-7506). They used the MOSFET's intrinsic JFET for the MOSFET drain above 7 - 10V. This naturally gives the rapid capacitance change, without requiring any switches or other nonlinear elements. This model was used for many of the Harris MOSFETs, now made by Fairchild, and it worked well, but I haven't seen it used for newly-introduced FETs.

Back to the Motorola approach. oops! oops! oops! I see that Motorola included two 10meg resistors in parallel with the capacitances, probably to help Spice converge more easily. These resistors aren't noticed working in the high-current regions Motorola had in mind. Fairchild has retained these in their newly-created models. I'll bet these intruders will cause an improper drain-to-gate current flow, that must be the gate current you complained about. Perhaps they can be removed entirely, or dramatically raised in value... You can try this, and I'll also be checking into it myself sometime soon.

--
 Thanks,
    - Win

Interesting! The JFET makes sense... basically modeling the body "gate". That's why my interest in data to fit to a Level=7 model... body effects are modeled.

...Jim Thompson

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|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
|  Analog/Mixed-Signal ASIC\'s and Discrete Systems  |    manus    |
|  Phoenix, Arizona            Voice:(480)460-2350  |             |
|  E-mail Address at Website     Fax:(480)460-2142  |  Brass Rat  |
|       http://www.analog-innovations.com           |    1962     |
             
I love to cook with wine.      Sometimes I even put it in the food.

Indeed.

But I don't know why RCA's MOSFET JFET model scheme isn't more popular. Looks like a natural. Wheatley and gang gave a number of conference papers and wrote three app notes on it in the early 90s, with lots of detail; they were promoting it.

--
 Thanks,
    - Win

As stated, I didn't modify the manufacturer's capacitance model.

Which leaves the dynamic capacitance model unsolved.

You'll find that most power MOSFETs have N in the 3 to 5.5 range. I've found that all the parts of a given type will have the same N but VTO varies from type-to-type, from batch to batch, and somewhat from part-to-part within a batch. You can quickly measure N with a few Vgs-vs-Id datapoints decades apart at low sub-threshold currents, and you can determine VTO (the gate threshold voltage) by plotting Vgs-vs-Id^1/2 at high currents (see AoE page 122) and extrapolating to zero current. I've found VTO from 1.5V to 5V for various MOSFETs.

I've also found that most linear use of power MOSFETs is below VTO. In this sub-threshold region the FET's performance is dictated by the classic exponential property, which depends only on Id, and not so much on the individual MOSFET (see above), and the variability of VTO = Vth only affects where the transition region occurs. But of course Vth is critical to DC biasing the part, which means a method of setting Id should be found that doesn't depend on Vth. It's the same issue we face in BJT circuits, really. It does appear that typical MOSFET Vth part-to-part variability isn't as bad as JFETs.

--
 Thanks,
    - Win

The actual FETs probably don't agree either, part-to-part. My careful pulsed high current measurements didn't precisely match the datasheet or any of the manufacturer's models. They did make good sqrt-Id plots however. You could trim VTO appropriately. I'd say, if it looks reasonable, go with it...

--
 Thanks,
    - Win

THe original model is bad; the modified one seems to act exactly the same. If i get rid of M2 and M3 and all the components associated with them, it works (DC). In your model, setting N=1.95 and VTO=3.65 gives a decent log slope that is seen in most (non-logic) power FETS. Took me a long time of fiddling with the 2 parameters to "match" that slope...

It was me that asked for Win to give us his model, so I feel obliged to do the check.

See the DC charactetristics result on ABSE.

As Win stated, Moto included 2 10Meg resistors to improve convergence. I commented them out and indeed had convergence issues with both models, but relaxing the ABSTOL up to 1nA solved them naturally. Deleting these resistors solves the gate current problem.

One point remains: the models don't agree on the high current region. Maybe Win had his model based on measured data for the high current region too.

--
Thanks,
Fred.