On those few occasions where I needed something like a UJT for anything but playing around, I found that their predictability was a problem and ended up using a regenerative NPN/PNP pair with base resistors setting the minimum "keep-conducting" current. Perhaps you can find a usuable solution along such lines rather than relying on the poorly specified properties of UJT's. Anymore, I think of them more as a curiosity than anything to keep in my mental toolbox of useful parts.
-- --Larry Brasfield email: donotspam_larry_brasfield@hotmail.com Above views may belong only to me.
I'm doing a job with an Onsemi 2N6027 Programmable Unijunction transistor. Haven't seen a UJT for years, and never used a PUJT. Forgotten everything.
The timing comps used in this circuit have a s/c current of 400uA, so I need a valley current that is reliably larger than that, up to 45C Tambient.
The Onsemi data sheet gives a few graphs, but don't really pin themselves down.
Is there an algorithm that relates the value of the valley current to Rg (and Vg, and possibly even Tamb)?
-- Tony Williams.
That's a pretty high valley current. Can you shut it down when the PUT triggers?
Best regards, Spehro Pefhany
-- "it's the network..." "The Journey is the reward" speff@interlog.com Info for manufacturers: http://www.trexon.com Embedded software/hardware/analog Info for designers: http://www.speff.com
Yuk. They do have a fairly high valley current (2N2646 4mA min).
That sounds more promising, and perhaps is a bit better at rejecting power supply noise.
What do you think?
VCC VCC | | .-. | | | | Rs | | \ | '-' - \ Zd | ^ +-------+ | | | Rx | | >| ___ | | |-+--|___|-+ | /| | | | | | | | | | | | | | .-. | | | | | Rs | | |/ | | --- +-| '-' --- |> | | | |
GND GND GND
I think that if there is a resistor Rx either where I show it above or in the K lead (to ground) the current is certainly limited. With Rx=0? Here's the SPICE model if you want to try modelling the currents.
..SUBCKT 2N6027 1 2 3
**************************************Q2 4 2 1 PMOD
..MODEL NMOD NPN(IS=5E-15 VAF=100 IKF=0.3 ISE=1.85E-12
..MODEL PMOD PNP(IS=2E-15 VAF=100 IKF=0.3 ISE=1.90E-12
..ENDS
It's been a very long time since I've worked with them, and even then, when we used many thousands, it was Ip that was of concern (typically
15M or higher timing components).Best regards, Spehro Pefhany
-- "it's the network..." "The Journey is the reward" speff@interlog.com Info for manufacturers: http://www.trexon.com Embedded software/hardware/analog Info for designers: http://www.speff.com
No. I'm stuck with what's there atm Speff, so have to try wriggling (probably at least until I can see about getting an old-fashioned UJT in there).
It's a 20V supply (with about 1.5mA spare), and Vg for the 2N6027 needs to be about 12V. A 5k+7k5 pot down would do 12V, with about 3k source resistance. That might give a valley current of 400uA under some circumstances, but not reliably, especially at 45C.
What would happen if the 7k5 were replaced with a 12V zener? That would have a few hundred ohms source-R, and the 2N6027 is guaranteed to have an Iv of 1mA with 200R source-R.
Or is it better to replace the 5k with an 8V zener, so that the source-R is low to the +ve supply?
Would that damage the 2N6027?
I don't know enough about PUJT's.
-- Tony Williams.
Ok, I think it is sussed now.......
When conducting, the Gate goes to 0v. When high values of Iv are required, the pullup current into the Gate has to be at least Iv*40 for the 2N6027.
--+--20v | --+--18.8V [470] | | | \_|_ Zener [45.7k] /_\ 6v2 | | +------+ |______G |A | | _\|__ | | \ /PUT | | _\_/_ | | |K | [12k] | ===C | | | --+--------+------+--0v
A 470 ohm pullup is roughly 28mA into the Gate, when the Gate is conducting at 0v. 28/40 should give a reliable Iv of 700uA at 25C, dropping to about 450uA at 50C ambient.
Now to look at the voltages and see why it is has a frequency only about 80% of the rough calcs.
Umm... see AoE, Fig 14.36, for the only discussion of Programmable Unijunctions that I could find.
-- Tony Williams.
You can see from my other post that the danger of Rx=0 was guessed at very quickly. The only spare holes in the pcb (ie, tidy, no hackings) allowed an Rx in series with the zener. I think this is an equivalent to what you suggested above.
Thanks for the model. I'll see if it can be converted and added to the LTSpice library.
-- Tony Williams.
I put this in the SYM subdirectory for the symbol and called it PUT.SYM:
-------------------------------------------- Version 4 SymbolType CELL LINE Normal 0 44 32 44 LINE Normal 0 20 32 20 LINE Normal 32 20 16 44 LINE Normal 0 20 16 44 LINE Normal 16 0 16 20 LINE Normal 16 44 16 64 LINE Normal -16 0 0 0 LINE Normal 0 0 8 20 WINDOW 0 44 11 Left 0 WINDOW 38 44 50 Left 0 SYMATTR SpiceModel 2N6028 SYMATTR Prefix X SYMATTR Description PUT for use with a model that you supply SYMATTR ModelFile PUT.LIB PIN 16 0 NONE 0 PINATTR PinName A PINATTR SpiceOrder 1 PIN -16 0 NONE 0 PINATTR PinName G PINATTR SpiceOrder 2 PIN 16 64 NONE 0 PINATTR PinName K PINATTR SpiceOrder 3
--------------------------------------------
I also put this in the SUB subdirectory for the model library the symbol uses and call it PUT.LIB.
-------------------------------------------- ..SUBCKT 2N6028 1 2 3
*Programable Unijunction Transistor *MODEL FORMAT: PSpice..SUBCKT 2N6027 1 2 3
*Programable Unijunction Transistor *MODEL FORMAT: PSpice--------------------------------------------
Hope that helps out.
You're not giving us much to go on- like why can't you reduce Ct to make the anode resistor more reasonable? -where is the output taken from and what amplitude do you want?- what frequency and stability?- what temperature range? I suppose that the best way to model the regeneration mechanism is with the "sinking load line" concept. Imagine the Va vs Ia curve with the negative resistance region dipping to Vv at Iv and continuing on into the saturation region. The external anode circuit at any instant will impose a load line on this characteristic going from Vcap on the Va axis to a pretty large Ia on that axis- so that for practical purposes, the load line is horizontal. This load line sinks down over time as the capacitor discharges and eventually intersects the PUT characteristic at (Iv, Vv). Now the trick is to maintain a negative sink rate on that load line through the intersection point- this is mathematically equivalent to requiring that the current through the anode resistor, say Ir, be Ir
It's the sawtooth generator for an ancient PWM field-coil driver. My end of the job was originally to do no more than replace the equally ancient 20A pnp darlington output transistor with something more bullet-proof.
But the front end doesn't work, so I'm having to investigate. That was the reason for the original PUJT question.
The (1KHz?) sawtooth is taken directly off the capacitor with a resistor network, whose values have to remain as-is until downstream scopings have been done. The loaded timing network reduces to an 18.8V source, with 45700 ohms and 0.022uF.
Rough calcs suggest that the raw sawtooth should be about 12v pk-pk, at about 1KHz. Frequency stability is probably not important, but it does run in a high ambient temperature.
That's a crafty one, using the Gate to get the Anode current below Iv. Never thought of that.
The 470 and 6v2 is working well enough atm, but that one is held in reserve. Thanks.
-- Tony Williams.
This topology can be adjusted to handle any situation where s/c current exceeds reasonable valley currents- nothing is especially critical at frequencies on the order of 1KHz, and high temperatures favor this ckt:
View in a fixed-width font such as Courier.
18.8V ,--------[27k]---------------. | | | | | e | | |/ | | ,-----------------| pnp [45.7k] | | |\ | | | | | | | +--------|----------+----+ +-[5.1k]-+-[5.1k]-G |A | | | | _\|__ | [220] | --- \ /PUT | | | - 12v _\_/_ | |/ | | |K +-[5.1k]-| npn | 0.022u | | | |\e ===C | | | | | | | [5.1k] | | | | | | | +-------------------+--------+----------+----+--0v
Yes. You an get rid of the PNP above and drive the NPN from the cathode of the 2N6027.
Best regards, Spehro Pefhany
-- "it's the network..." "The Journey is the reward" speff@interlog.com Info for manufacturers: http://www.trexon.com Embedded software/hardware/analog Info for designers: http://www.speff.com
Since the pnp is const-I that 5.1k in series with the base of the npn is probably not needed.
When using an external discharge transistor, does the PUT get forced off when the transistor takes the A-K voltage below the forward drop of the PUT? Similar to commutating an SCR?
-- Tony Williams.
Yup. This is very close to a chunk of a commercial product we used to make.
Best regards, Spehro Pefhany
-- "it's the network..." "The Journey is the reward" speff@interlog.com Info for manufacturers: http://www.trexon.com Embedded software/hardware/analog Info for designers: http://www.speff.com
You're probably right. The main limit points for the npn drive are that it support a current of >>(18.8-Vak)/45.7K=400uA when Vak=Vf@Iv=~0.8V, and that npn beta,max x Ib 0.8V. The pnp drive is 200uA, so if you replace that 5.1k+5.1K with a 10K from base to GND, this will produce a base drive of (200uA x 10K-0.7V)/10K=130uA so that even at beta=150 Ic=20mA which is 400uA/30uA=15.
Right, it is more that the transistor is shunting away anode current required to support PUT saturation region operation - since (18.8-Vak)/45.7K is negligible compared to the npn and PUT currents, the capacitor is discharged by the PUT and npn to 0.8V and
-CdV/dt=Iv+Ic,npn. Since the npn is now saturated at ~3mA (it did not sink enough current for an earlier intercept where the PUT Ia>50mA for Vf=0.8V), dV/dt=(500uA+3mA)/0.022u=160mV/us at Iv=500uA or (50uA +
3mA)/0.022u=140mV/us at Iv=50uA, so that in each case the PUT enters the negative resistance region with a strong negative dVak/dt and the variation over a 10:1 Iv range is
I don't trust that approach because it doesn't work for Iv=0, you can't continue to drive the NPN when there's no IAK- plus you have that overhead from the 45.7K to think about and there is a complicated Vk vs Ct characteristic if you contemplate overdriving the NPN into saturation and rely on storage time for shut-off. This will *never* fail:
View in a fixed-width font such as Courier.
. .. . .. 18.8V .. ,--------[27k]------. | .. | | | .. | e [45.7k] .. | |/ | .. | ,-----| pnp | .. | | |\ +-[220]---+-------+ .. | | | | | | .. | | | | | | .. +-10k--+--+-[5.1k]-+-[5.1k]--------------G |A | .. | | | | | _\|__ | .. | | | | | \ /PUT | .. | | | | |/ _\_/_ | .. | | | +---| npn |K | 0.022u .. --- | | | |\e | ===C .. - 20V | === | | | | .. | 15k |0.1u [10k] | | | .. | | | | | | | .. +------+--+----------------+-----+---------+-------+--0v . ..
Whoops- forgot about the gate drive- this will be a mA or so- but how to protect against large Iak at turn-on. You would want to do something this- but now the discharge is to about 1.8V instead of 0.8. View in a fixed-width font such as Courier.
. .. . .. 18.8V .. | .. | .. | .. | .. [45.7k] .. | .. | .. +---------------------+----+ .. +---10k----+--[10k]---G |A | | .. | | _\|__ [220] | .. | | \ /PUT | | .. | +---+ _\_/_ | | .. | | | |K |/ | 0.022u .. --- | | +---------[1k]------| npn ===C .. - 20V | === | |\e | .. | 15k |0.1u [1k] | | .. | | | | | | .. +----------+---+--------+---------------------+----+--0v . ..
Actually- the simulation shows the capacitor discharging to 0.25V- you can see Vanode dropping abruptly to 1.1V and then a 40us reduced slope to 0.25V before the capacitor begins recovery. So it looks pretty good.
Hmmm- you definitely need the gate current to keep that NPN on - reducing the K resistor to 100 ohms shows the PUT latching on- so that's a down side. I think you're safe relying on G-K storage recovery to keep it going- and you have added ~1K x 0.022u=80us to the oscillation period.
It looks like one requirement is to use a decoupled Rg that is large compared to Rk which ensures that the NPN is cutoff at the half-way point of Vg recovery to 12V at a maximum- that terminal shows a very long recovery time within a few volts of 12V. Then a worst case cutoff of Vk=0.5 means Vg=12V-0.5/Rk*Rg, so that Rg/Rk=10 puts worst case cutoff at Vg=7V and typical at 6V. You also have that Vg=12-(Ib,npn*2K+0.7V)*Rg/Rk which is a very strong gain, 20,000 , making for a large VGA reverse bias by the time the NPN stops sinking the 400uA through the 45.7K to 18.8V. The source resistance of the 12V divider needs to be halved to prevent hangup at turn-on if the 18.8V comes up before the 20V for some reason. View in a fixed-width font such as Courier.
. .. . .. 18.8V .. | .. | .. | .. | .. [45.7k] .. | .. | .. +------------+------+ .. +--5.1k-+---+-[10k]---G |A | | .. | | | _\|__ [220] | .. | | | \ /PUT | | .. | | | _\_/_ | | .. | | | |K |/ | 0.022u .. --- | | +---[1k]---| npn ===C .. - 20V | === | |\e | .. | 7.5k |0.1u [1k] | | .. | | | | | | .. +-------+---+-----------+------------+------+--0v . ..
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