problem with PCIe parallel port in EPP mode

That's a horrible performance hit. Ick! ...and if both happen to have dirty copies of the same address?

...or memory is coherent.

TLBs are a different kettle o fish.

In a retarded architecture, perhaps. In any sane architecture, main memory is kept coherent.

Reply to
krw
Loading thread data ...

On Sun, 24 Apr 2016 18:34:32 -0400, krw Gave us:

A computer would not compute otherwise.

Danger, Will Robinson.

Well, maybe a quantum computer could still get the right answer.

formatting link

Reply to
DecadentLinuxUserNumeroUno

The memory model Clifford describes isn't, AlwaysWrong.

AlwaysWrong, why don't comment about something you actually understand?

Reply to
krw

They don't (shouldn't) as a matter of policy. That is handled by O/S memory mapping, and by threads using locked instructions where they need coherence. This kind of threading is a difficult programming model. I've only done one major project this way, and would almost always find a way to avoid the need to.

You're almost three decades out of date with that approach.

The last high-performance MP CPU that attempted to keep all of main memory coherent was probably built in the 1980's. It simply isn't possible to keep large low-ns cache coherent - it just defeats the purpose of having a cache at all.

Clifford Heath.

Reply to
Clifford Heath

Oh, that's comforting.

Bad plan and completely unnecessary.

Wrong.

You're wrong. Shall we start calling you "Decadent"?

Reply to
krw

Not always... but mostly I agree. This difficult stuff should be relegated to shared system services that cannot live without it, such as high-perf graphics libraries and DBMS.

Happy to hear evidence to the contrary. Multi-core has changed things.

Reply to
Clifford Heath

On Sun, 24 Apr 2016 19:51:20 -0400, krw Gave us:

Nice try, punk.

Reply to
DecadentLinuxUserNumeroUno

No, you really didn't even try, AlwaysWrong. You never do.

Reply to
krw

PowerPC. Nope.

Reply to
krw

On Mon, 25 Apr 2016 12:33:22 -0400, krw Gave us:

The Cell CPU.

Again, you are not very bright.

Reply to
DecadentLinuxUserNumeroUno

No, I didn't work on cell so really don't know how they work. '750 and '970.

Perhaps but right beats bright, in this case.

Reply to
krw

That is true, but it doesn't apply here, because you aren't right.

Otherwise why does PowerPC have sync/msync instructions? See page 23 here:

You don't need cache control instructions in a coherent-memory architecture.

Clifford Heath.

Reply to
Clifford Heath

On Tue, 26 Apr 2016 09:27:40 +1000, Clifford Heath Gave us:

I am sure that will go right over his antiquated API head, as he has limited understanding of even his wee wittle bwain's limited instruction set.

Danger, Will Robinson.

Reply to
DecadentLinuxUserNumeroUno

And, I just got another cheap PCIe parallel port card from China, that is even less functional than the Oxford chipset one. This one behaves like it has no EPP funtionality at all. PCI enumeration lists it as serial only, but it seems to do SPP/Bidir, too.

So, right now, I only know of ONE PCIe plug in card that works, with the MosChip 9900. This appears to be going obsolete, now there's the MosChip

9901. I will have to test that one, hopefully they didn't break any functionality.

Jon

Reply to
Jon Elson

Is this the one?

formatting link

John

Reply to
jrwalliker

Yup, the one with the chip mounted at 45 degrees is the one that I have shown to work in all modes. I probably need to get a sample of the newer one with the MCS9901 chip and find out if it works, too.

Jon

Reply to
Jon Elson

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.