PRBS in LT Spice

John Larkin · 2012-10-13T15:50:12+00:00

We are considering sending data over CAT6 twisted-pairs, from one FPGA to another at some 10s of meters distance. It might be prudent to transformer-couple the data, to avoid ground-loop common-mode hazards, and the obvious choice would be to use RJ45 connectors with built-in Ethernet magnetics. These seem to have inductance in the 400 uH range, which gives a low-end frequency response in the 40 KHz sort of range. The data would have to be DC-balanced, and we'd have to use NRZI coding, bit filling, whatever to avoid long runs of 1s or 0s from adding any low-frequency components. We have 80 or so streams arriving at the main FPGA from the field, so we may not have enough FPGA resources to do full 8b10b or some such encoding; we may have to invent something dumber. Our bit rates will be in the 25-125 mbps sort of range. Anyhow, I started playing with pushing uncoded pseudo-random data through the magnetics. I used the standard LT Spice "digital" parts and found that they would NOT make a working shift register. I had to edit all the flops to add the "TD=1n" Spice directive to give them some prop delay. The RC lowpass filter below gives a quick visual indication of the sequence periodicity. The sequence taps are from AoE page 657. Version 4 SHEET 1 3280 884 WIRE 96 -320 48 -320 WIRE 160 -320 96 -320 WIRE 160 -272 -592 -272 WIRE 720 -272 336 -272 WIRE 720 -32 720 -272 WIRE 720 -32 624 -32 WIRE 560 -16 -496 -16 WIRE 1616 -16 624 -16 WIRE 1712 -16 1616 -16 WIRE 1856 -16 1712 -16 WIRE 2064 -16 1936 -16 WIRE 2128 -16 2064 -16 WIRE 2176 -16 2128 -16 WIRE 1392 0 624 0 WIRE 2064 64 2064 -16 WIRE 2064 208 2064 128 WIRE -496 352 -496 -16 WIRE -432 352 -496 352 WIRE -96 352 -272 352 WIRE 208 352 64 352 WIRE 512 352 368 352 WIRE 832 352 672 352 WIRE 1152 352 992 352 WIRE 1392 352 1392 0 WIRE 1392 352 1312 352 WIRE 1472 352 1392 352 WIRE 1712 352 1712 -16 WIRE 1712 352 1632 352 WIRE 1824 352 1712 352 WIRE 2064 352 1904 352 WIRE 2352 352 2176 352 WIRE 2416 352 2352 352 WIRE 2464 352...

Oct 13, 2012 23 Replies

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John Larkin 13 years ago

Right!

I guess, when people design real flipflops, they usually make sure that a shift register will work.

John Larkin Highland Technology, Inc jlarkin at highlandtechnology dot com http://www.highlandtechnology.com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom laser drivers and controllers Photonics and fiberoptic TTL data links VME thermocouple, LVDT, synchro acquisition and simulation

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josephkk 13 years ago

across

At that speed try B3ZS (a derivative of alternate mark inversion [AMI])

?-)

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Allan Herriman 13 years ago

across

I wrote a B3ZS core sometime last century and released it on opencores.org about a decade back.

formatting link

Regards, Allan

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John Larkin 13 years ago

Interesting; thanks. We do need something relatively simple to map our baseband data into something with no lf/dc components.

John Larkin Highland Technology Inc www.highlandtechnology.com jlarkin at highlandtechnology dot com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom timing and laser controllers Photonics and fiberoptic TTL data links VME analog, thermocouple, LVDT, synchro, tachometer Multichannel arbitrary waveform generators

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