A power design is using the circuit in Fig 2 with some small changes. A 10 K series resistor is added to the E1 input and a second FET is added to Q1 to block current flow in both directions when off.
The designer needs to provide a logic signal to indicate input power failur e. The power board designer is tapping the H2- signal which never rises mu ch above the 1.25 volt threshold as the indicator and intends for us to use a comparator to detect the change.
My thinking is to make the series resistor on E1 into a divider at a voltag e just below the other two trip points. This will allow H1 to be a dedicat ed pull down output with as much voltage differential as we desire to imple ment.
I have trouble understanding the operation of this chip. It is actually fa irly complex. I expect E1 to go inactive anyway, just not as soon since th e external supply likely has a large cap and will not ramp down to 1.25V so quickly. So is there anything I am missing in how these enable inputs wor k? Will removing E1 cause any issues with the switchover?