A PCI Express master (a "root complex") generates a 100 MHz reference clock to target devices. In some cases that we've observed, the master (in this case, an AMI based motherboard) ramps the clock down to 12.5 MHz, in apparently a smooth transition, like a PLL being cranked down.
We can find no reference as to when, and why, the ref clock would be stepped down in frequency, or what might bring it back up. Does anybody know anything about this?