A PCI Express master (a "root complex") generates a 100 MHz reference clock to target devices. In some cases that we've observed, the master (in this case, an AMI based motherboard) ramps the clock down to 12.5 MHz, in apparently a smooth transition, like a PLL being cranked down.
We can find no reference as to when, and why, the ref clock would be stepped down in frequency, or what might bring it back up. Does anybody know anything about this?
got to do with Active State Power Management (ASPM) ?
-Lasse
Intel (and all the other references we can find) talks about "removing" the clock in shutdown states, to save power. It looks like only the AMD chipset ramps it down to about 12 MHz in the L1 powerdown state. That's weird, and we can't find any mention of it anywhere.
Maybe this keeps the coupling caps halfway charged up and speeds return to operating states. Or something.
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