Overvoltage protection for sensitive device

10-15sec is a long time. First, most resistors aren't spec'd for more than 150-200V although you can get higher voltage versions from companies like Vishay. Then, take a look at the dissipation. Proper protection requires clamping diodes after that resistor so lets say they clamp at 20V, then the other 3980V are dropped across the input series resistance. Let's say you have 10K in there: 3980V^2/10kohms = more than 1.5 kilowatts ... one second ... two seconds ... phssst ... phooof ... *BANG*

Somehow this calls for a totally isolated design.

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Regards, Joerg

http://www.analogconsultants.com/

Thanks, Joerg

what about spark gaps ? I suppose all nominal spark gap voltages are too high ? Device which I am trying to protect is not my design so I mentioned 20-30 Volts just out of precaution. I suppose I can get to max. 200 V. Is there a solution with spark gap only ?

I must mention that tests are for electrostatic charge, so they cannot provide such currents.

Perhaps you could explain more about the test.

An electrostatic discharge event is over in nanoseconds, so how do you get to 10 seconds? Or do you mean there are multiple discharges for 10 seconds? Is this one of the a standard "human body model" or "machine model" tests?

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John Devereux

Generally, no. Spark gap performance varies greatly with tolerances, humidity and so on.

Well, that won't be 10-15sec. All you need is to survive a few dumps from a pre-charged (small) capacitor. You'd have to provide more info in order to help, maybe post a schematic.

The usual method for inputs is a series resistor and clamp diodes to the rails, then another smaller resistor to the pin of the chip. Or a transient voltage suppressor (TVS). Outputs can really only be handled with TVS unless it's not a very low impedance output.

However, you might want to gently mention to your bosses that in order to make an existing design not fail ESD a re-design is usually required. You can get there with rework but it'll be ugly and production will most definitely not like that.

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Regards, Joerg

http://www.analogconsultants.com/

4-5 KV for 15 seconds? SECONDS? That would require one hell of a high input inpedence to avoid letting a lot of magic smoke out.

On a sunny day (Thu, 11 Dec 2008 14:33:24 -0500) it happened PeterD wrote in :

That was sort of the standard test for isolation between mains primary and secondary for transformers. That has nothing to do with inputs.

If they tested the input that way versus mains or ground, possible, but not the way the test should be done. The OP will have to be a lot more specific before any suggestion can be made.

If you want a sensible answer you must provide a schematic of the test circuit (eg. 100pF charged to 4kV with 1K5 in series) and explain more about your input circuit and source characteristics so we can understand how much series and shunt impedance and leakage current you can tolerate. Otherwise we're just guessing.

That looks also absurd to me, testing inputs with 4 kV. What is more absurd, the device is robust in design and always worked flawlessly and now is threatened to be discarded by security and quality standards.

I do not have any schematic here, I will contact engineers about that.

Thanks.