Oscillators at GHz frequencies -- question

awsome. thanks

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The transistor was biased in the standard way for Vc = 0.5Vcc and Ve =

ely the S, Z matrix etc., come

The netlist is below. Beta(min) for the BFQ65 is 60, and Ic(max)=50 mA, s o Ic value selected for this design is 35 mA. Vcc is 12V. A separate C prog ram calculates all the biasing resistor values, PI network capacitor, input , output capacitor values, SPICE transient analysis sampling time etc.,

.SUBCKT BFQ67W 1 2 3 Q1 6 5 7 7 BFQ65

• SOT323 parasitic model Lb 4 5 0.6n Le 7 8 0.6n L1 2 4 0.34n L2 1 6 0.1n L3 3 8 0.34n Ccb 4 6 100f Cbe 4 8 2f

.MODEL BFQ65 NPN(IS=5.56440E-16

• BF=1.70000E+2 NF=0.994874
• VAF=48.0334 IKF=0.918182
• ISE=1.04797E-14 NE=1.47947
• BR=1.42108E+002 NR=9.94125E-001
• VAR=2.55564 IKR=9.63277
• ISC=4.38252E-16 NC=1.08948
• RB=10.0 IRB=1.0E-6
• RBM=10 RE=0.655965
• RC=2.0 EG=1.11
• XTI=3.0 CJE=1.13769E-12
• VJE=0.6 MJE=2.49462E-1
• TF=1.19796E-11 XTF=2.59987E+1
• VTF=1.22309E+0 ITF=1.97376E-1
• PTF=1.00348E+1 CJC=5.15977E-13
• VJC=1.55871E-10)

.PARAMS C0=2.253867e-12 CBYP=1.769e-11

• CIN=3.065e-12 COUT=2.653e-12
• L0=1.00e-08 AMPL1=12 RB0=115.789 RL=50.00K
• RB1=263.159 RC=200.00 RE=60.00 TS=4.444e-11

.SUBCKT ampcomemitter 1 2 3 7

.SUBCKT PIN 1 2 3

VCC 1 0 DC {AMPL1} AC 0.0 C0 3 4 {COUT} R1 4 0 {RL} XCEA 1 2 3 0 ampcomemitter XPI 4 2 0 PIN

.OPTIONS METHOD=GEAR NOPAGE RELTOL=1m MINBREAK=5ps

The output is wierd.

As a followup....

I would strongly suggest that you look at a differential oscillator. These are de-facto *the* standard topology in asic design. Its gain is much better than a single transistor Colpitts etc, of which, essentially, no one uses in those aforementioned billions and billions of products. Pretty much only xtal oscillators use single ended oscillators in asic products.

The concept is shown here:

Unfortunately, and very sadly, the only other asic poster that regular posted to this NG (Jim Thompson), is no longer with us it would seem. The point here is that, techniques that are actually the norm, i.e most used by sheer numbers, are not typically used for board level design, which is most of the experience, I believe, in this NG.

-- Kevin Aylward

JT posted a differential oscillator in LTSpice format several years back when I was simulating a lot of oscillators. It was quite informative, but it worked *really badly* compared to what I already had. He also posted one with AGC, again an interesting topology, except the AGC was biassed wrong and was doing nothing; the amplitude was actually controlled by limiting. I managed to fix his AGC circuit, but I never built the diff osc.

Clifford Heath.

It is very easy to take a good topology, and make it work badly...

I would repeat that the differential topology is pretty much a/the standard for non-xtal oscillators in asic products. The higher gain is a strong decider.

AGC is usually much more agro than its worth. A basic issue, is that just adds more noise.

Yes. Very, very common for circuits to be working not in the manner that they are believed to be working.

I might have a go at creating an example for my yearly SS update...

-- Kevin Aylward

I wonder how much and in what way does the ASIC technology limit the oscillator performance. Discretes may have some other problems or limits. And low voltage is common to both. How to get the best is IMO more interesting than the technology.

If you don't tell us the values {RC}... we can't have a look at this. In the meantime:

- Do you really need to specify those initial conditions (60V, 36V, 100V)?

- Why is the time step limited to 1us for an oscillator operating at GHz frequencies?

Pere

on the plus side, there is essentially, no inductance... on the negative side, there are essentially, no inductors....

I would have thought the advantages of ASICs for high frequency were pretty apparent. No transmission line parasitics, no cap parasitics, no inductor parasitcs, digital tuning. As far as the "oscillator" goes an ASIC oscillator may well have several internal ldos, chebychev temperature compensation, varactor linearization, clipped sine and cmos output buffers etc... etc... Its a no brainer. Typically an oscillator asic will have like

-- Kevin Aylward

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m. The transistor was biased in the standard way for Vc = 0.5Vcc and Ve = 0.1Vcc. It also

iately the S, Z matrix etc., come

A, so Ic value selected for this design is 35 mA. Vcc is 12V. A separate C program calculates all the biasing resistor values, PI network capacitor, i nput, output capacitor values, SPICE transient analysis sampling time etc.,

Please take a look at the .PARAMS directive at the top of the netlist. All values are listed there. I have tried larger time durations fort the .TRAN analysis, but that does niot make any difference.