I have a USB-powered board which draws a lot of inrush current (close to 1A) on startup. This leads to problems with the USB interface with the computer and also the voltage level droop seen by the devices on the board. Now I am faced with the task of figuring out a way to solve this problem but I have no clue over how to go about it.
The board has an FPGA, a microcontroller, SRAMs, EPROM, and plenty of discreet components. No power sequencing is done and all the regulators turn on at the same time. The board has a TPS2014 which helps limiting inrush but seems is not enough.
How do I go about optimizing the values of bypass caps to reduce inrush while maintaining their bypass function? Is there a way to simulate that? Are there other ways? Power sequencing is a bit difficult because the FPGA uses 3 supplies.
Thank you.