OpAmp compensation

A good book on opamps can be found at

Given the PSRR of the data converter, you need to get the supply noise down to 300uVpp. A TPS79650 does 40uVrms. Close enough for government work. That's just a datasheet I had handy. I didn't do a search.

Incidentally, not only would you need to compensate the network, but you would have to do it in a manner where it doesn't increase the PSRR of the regulator.

Why did you start off with such a gawd awful regulator topology in the first place?

If the goal is a low noise supply, giving the op-amp a way to control the voltage in a more first hand way would be much better. Having it control a common source MOSFET sinking current from the rails means that it is controlling the voltage fairly indirectly. At high frequencies, it basically loses control on the voltage because it can't vary the MOSFET quickly.

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You also want to compensate in a manner where as the op amp loses bandwidth, the cap is holding the gate of the mosfet such that it tracks ground, not the supply rail. When designed properly, the feed through of a LDO reduces to a capacitive divider comprising the Cds of the pass device and the load cap.

I'm not a big fan of having lots of DC gain in regulator designs. Few people care about the DC regulation as much as the transient regulation. In the LDO chips I've designed, I never had more than one gain stage in the error amp. This is especially the case for P-fet pass devices, which themselves can look like a gain device under the right conditions.

Really, just buy a freakin' LDO and keep the analog guys in the money.

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I disagree with the gate following ground. It would be better if it went to the gate following the output. The MOSFET is working as a shunt regulator. Making its gate follow the drain makes its output impedance low at high frequencies.

The topology is just a bad one, however, so doing a careful detailed design isn't really worth the bother. You can make a better regulator with fewer parts.

The things that I end up caring about way too often are the frequency the dam thing oscillates at when the output side sees a good quality capacitor and the low maximum voltage spec. Having to add a bunch of over voltage protection and resistors in series with the output side makes it easier to do my own.

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Regarding compensation, I wasn't thinking about this goofy design but more typical LDOs, i.e. a pass device rather than a shunt. With a pass device, once the amp is dead (lack of bandwidth), all you have is the pass fet and the load. The pass element has a capacitive coupling path, and thus forms a cap divider.

Regarding high quality caps causing instability, that leads to my rant about having too much gain in the error amp. You get DC accuracy that is plain silly, but cause AC headaches.

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Even when the op-amp is driving a P-MOSFET, we can do better. Consider a circuit like this over simplification:

s d ------------+------- --------+---------------+-- Load ! ! ! ! ! ! ! =3D=3D=3D=3D=3D=3D=3D ! Feedback ! ! \\ --/\\/\\---+ / R2 ! \\ R1 !/ ! opamp---! Q1 =3D=3D=3D C1 !\\e ! R3 -----------+-----/\\/\\---GND

When the op-amp runs out of steam, the R1-C1 path is mostly what is setting the gain of the Q1 stage. So long as you keep the gain of that path low enough, you can't get oscillations from that path but you still get a reduction in the zout of the MOSFET

Hi,

I choose this topology, because I would like to keep varying load currents out of the supply rails. With this topology there is only DC current on the rails, and the fluctuating currents are only in small loops close to the consumers (given that the regulator is placed close to the consumer). An added advantage is with the use of opamps which have no short-circuit protection on their outputs, they are limited to the current set by the current source.

Regards,

Remco Poelstra

I've used shunt regulators internally in chips for the same reason. Well, specifically for PSRR, but similar to what you are trying to do. Generally for a bootstreaped bandgap, where burning a bit of power isn't an issue.

I still don't like using the op amp. There are shunt regulator chips. Two gain stages means you need a Miller, while one gain stage is generally compensated with a cap to ground. The Miller cap can be a source of poor PSRR. You don't need a microvolt of DC regulation, so you don't need two gain stages.

If you insist on the shunt, be sure that it don't overvoltage the downstream circuitry (load) on start-up. You need to insure the shunt wakes-up as low impendance so the out starts from ground and rises to the regulated voltage. Also ramp the raw supply up and down in a transient to insure it doesn't overvoltage in that case too. I've had occasions where I would need to put in a diode to the raw power to insure that if it is up, then shorted, then back up again, the compensation cap gets discharge on during the grounded phase.

There is a lot of good engineering in chips that often gets skipped when someone tries to rolll their own. Protection circuitry is generally what gets skimped in discrete designs.

In that case you a PNP as the sink and the circuit will be less awful. The PNP naturally is low noise and low impedance. The indirect control of the voltage by controlling the MOSFET is just a bad idea.

How can I do the same trick without the opamp? I need some kind of error amplifier no?

The shunt regulators that I found all had quite high noise, at least when compared to ICs like the ADR440. Is there a specific IC I missed?

Regards,

Remco Poelstra

I've tried both with a MOSFET and BJT (shouldn't it be an NPN?). I knew the BJT had less noise, but at first I couldn't get it to work with the BJT, so I tried the MOSFET. I don't get the point of your last sentence; When I use a BJT, the voltage is still controlled indirectly, no?

Regards,

Remco Poelstra

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No. I want you to correctly use the PNP It looks like this: Current source V ! +---------+-------- Load ! ! -----!+\\ R1 !/e ! ! >-+-/\\/\\---! PNP ! ---!-/ ! !\\ ! ! =3D=3D=3DC1 ----GND ! ! ! ! +--------+----/\\/\\------------ ! R3 \\ R2 / \\ ! GND

R1 is something like 51 ohms. It is just to prevent oscillations in the PNP as some high RF frequency.

C1 and R2//R3 close the loop around the op-amp near the point where the gain bandwidth of the op-amp is hit so that the op-amp doesn't oscillate or have a noise peak.

The PNP continues to provide a lowish impedance to the load side well above the frequency where the op-amp runs out of gain. The PNP is natuarally low noise so the high frequency noise performance is ok.

Beyond me. I'm an IC guy. If money isn't a problem, you could use any shunt then follow it up with that LTC part.

I'm sure you've seen this insanity:

The noise you quote is just that of the ADR440. You haven't computed the noise of the whole circuit.

Your problem is you need about 30ma for the regulator, and there are not many shunt regulators that high.

Maybe you can parallel two LM4050 s with ballast resistors. They are relatively quiet.

Sorry, I don't get your point. What do you mean with 'LTC part'?

No, I hadn't :)

True, but I first like to get the circuit operate correctly before doing the noise math and perhaps improve on that one.

Regards,

Remco Poelstra

I see, the PNP upside down :). Seems about time to get a good book on BJT's, because I don't see why this gives a low impedance path for high frequencies. I'll try this one though to check whether it works. Am I correct when I say that the opamp controls the output voltage more direct in this case, because there is only the constant +-0.7V offset from the Vbe? Can I then also conclude that the second stage has low gain in this configuration?

Regards,

Remco Poelstra

The PNP provides a voltage gain just a little under one. It provides a current gain equal to its HFE. This means that the emitter leg shows an impedance of about:

Z =3D (0.025/Ie) + ( 51 + Z(opamp) ) /100

The 25mV number is about right at room temperature of silicon. 51 is my 51 Ohm resistor. Z(opamp) is the output impedance of the op-amp circuit with the capacitors effect included. The 100 is the HFE. The feedback through R3 and the gain of the op-amp reduces the impedance from this value at frequencies where the op-amp has gain.

We can ignore the resistances of the PNP. They aren't going to add enough noise to matter. At high frequencies, the noise current in the current sense resistor is going to start to matter but by time you get up there the bypass capacitors will have a very low impedance.

The "constant 0.7" is really only a rough number for a silicon junction running at a highish current.

Actually a TI part. Shunt regulator then follow up with a quiet LDO and you are done.