OPA552 as power regulator

Why not the time tested complementary npn-pnp on the output with the base t o emitter resistor that kicks them into conduction when the current surges above say 50mA, and the OA handles the small stuff. Then you offload the po wer into components that presumably are packaged to handle it. Actually the 20R you have there now is about right.

The cap closes the feedback loop local to the opamp, at high frequencies, so the extra pole of the big output cap doen't make the closed loop unstable. That's pretty common. Win discusses that config in AoE3 p 264. I tweaked that concept a bit to let me use the undercomp amp that we have in stock; it could oscillate if the HF feedback had unity gain.

It simulates nicely. Spice sims are usually spot on for simple stuff like this, but I didn't expect the oscillation in slewing current limit. Maybe it's a limit-cycle thing.

He does? The feedback resistor from the output usually joins to the OA IN(-) and not the inner feedback R+C zero. And you're not compensating for the OA since your gain is large enough. You're compensating for that dominant pole on the output.

I wouldn't believe the sim. Are you using the TI model of the 552?

As noted, the OPA552 is not unity-gain stable, so it makes sense to jam in the fast feedback before the gain-set divider.

That's just a lot of words. I designed it to work, and it does.

Yes. One of my kids imported it into LT Spice for me. He used the auto-generated symbol for the opamp, and that's ugly.

I've done this sort of opamp rail supply many times. It always works. Actually, I usually do the compensation and parts values in my head, and that always works. All you need is a big safe distance between the poles, and a giant output cap to hold up the load.

We often need goofy-voltage bypassed rails, more for Vcm references and such than actual power. This topology works fine.

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You're compensating for that dominant pole on the output.

That 20 + 20 u alone breaks at 2500 Hz, that's not a lot of words, and the output resistance of the OA probably makes it 1000Hz. The OA actually has a pretty clean phase/frequency, looks like a perfect integrator out to 1MHz before the higher frequency internals start cutting in. Did you run a gain/ phase on the TI model to see if it resembles fig 2 of the datasheet?

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My guy made an inverting -1 gain amp in LT Spice, and the frequency response peaked right where it should have. The model looks OK.

If anything is wrong with the loop comp, which is unlikely, I could always change a couple part values. If the amp or the circuit topology or the thermals were wrong, that would be a lot more serious. We always try to sell rev A, but an ECO or two is no big deal.

The most common problem with parts from unknown sources in China is when th ey turn out to be salvaged parts remarked as something else. With your fets you could determine they were what they claimed, that's not always so easy . But yes, if you don't need traceability or a trustworthy supplier you can get a lot for a little.

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makes it 1000Hz. The OA actually has a pretty clean phase/frequency, looks like a perfect integrator out to 1MHz before the higher frequency internal s start cutting in. Did you run a gain/phase on the TI model to see if it r esembles fig 2 of the datasheet?

Something isn't right because if you don't compensate for that low frequenc y output pole, the entire sense of the amplifier is inverted. Does LTSpice do a noise gain analysis? You should run it.

I could make the current limit a function of the supply voltage, or of the programmed output voltage.

I could drive it from a DAC, but that would take more parts, and code.

C1 fixes the loop stability problem. My current version has C1=1uF, but I was surprised that it behaves well at 1 pF, which is really a placeholder for zero.

Step response is clean, so it's stable.

TI doesn't give a schematic of the amp internals. Some opamps bury their dominant pole deep inside, so get unstable in circuits like this where an external pole is added to the loop. But some hang one end of the comp cap on the output pin, so capacitive loads change that internal rolloff, and they tolerate c-loads. A few opamps, like LM8261, tolerate any capacitive load.

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ency output pole, the entire sense of the amplifier is inverted. Does LTSpi ce do a noise gain analysis? You should run it.

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I limited the DAC slew rate so as to not current limit big swings into

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equency output pole, the entire sense of the amplifier is inverted. Does LT Spice do a noise gain analysis? You should run it.

Yours won't, you have 70o phase margin judging from fig2. of the datasheet. Probe the top of R5 for feedback gain/phase to input:

Version 4 SHEET 1 880 680 WIRE 0 32 -64 32 WIRE 144 32 80 32 WIRE 208 32 144 32 WIRE 448 32 288 32 WIRE 144 64 144 32 WIRE -64 160 -64 32 WIRE 144 160 144 128 WIRE 208 160 144 160 WIRE 352 160 288 160 WIRE 448 160 448 32 WIRE 448 160 352 160 WIRE 144 176 144 160 WIRE -64 288 -64 240 WIRE 144 288 144 256 WIRE 144 288 -64 288 WIRE 352 288 352 240 WIRE 352 288 144 288 WIRE 448 288 448 224 WIRE 448 288 352 288 WIRE 144 336 144 288 FLAG 144 336 0 SYMBOL res 192 176 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 0 56 VBottom 2 SYMATTR InstName R1 SYMATTR Value 10 SYMBOL res 336 144 R0 SYMATTR InstName R2 SYMATTR Value 200 SYMBOL res 192 48 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 0 56 VBottom 2 SYMATTR InstName R3 SYMATTR Value 1k SYMBOL res -16 48 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 0 56 VBottom 2 SYMATTR InstName R4 SYMATTR Value 8k SYMBOL res -48 144 M0 SYMATTR InstName R5 SYMATTR Value 1k SYMBOL cap 128 64 R0 SYMATTR InstName C1

SYMBOL cap 432 160 R0 SYMATTR InstName C2

SYMBOL voltage 144 160 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V1 SYMATTR Value AC 1 TEXT 224 320 Left 2 !.ac dec 100 10 100k

Really flat feedback gain at -20dB and non existent to negligible phase shi ft.

In my two examples, what I needed was the unobtainium performance. If they had been salvaged parts, but worked, I probably would have been happy. Here, the obscure nature of the parts, the low selling price, and the fast delivery all argue against remarking, etc.

I forgot to mention, in both cases my 250 pieces came sealed in their proper machine-assembly tape.

Not clear if Fig 2 is of much help, it's made w/o high cap load. What John ought to do, is simply run an open-loop-gain Bode plot, with his load, make his own Fig 2, see what the phase margin is.

The transient response is more useful than a Bode plot. It gets more interesting when it's nonlinear. I saw an oscillation of the OPA552 circuit when it was slewing hard.

Since my load will be pulsed, I'll do some pulse-loading sims too. But with 100uF, or even 20 uF, on the output, and microsecond pulses, I don't expect much to happen.

It only gets better when OA input capacitance and output impedance are adde d. It looks like the very large separation between the significant poles he lps a lot. Is there some other effect you have in mind?

Version 4 SHEET 1 880 680 WIRE 0 32 -64 32 WIRE 144 32 80 32 WIRE 208 32 144 32 WIRE 448 32 288 32 WIRE 144 64 144 32 WIRE -64 128 -64 32 WIRE 16 128 -64 128 WIRE -64 160 -64 128 WIRE 16 160 16 128 WIRE 144 160 144 128 WIRE 208 160 144 160 WIRE 352 160 288 160 WIRE 448 160 448 32 WIRE 448 160 352 160 WIRE 144 176 144 160 WIRE -64 288 -64 240 WIRE 16 288 16 224 WIRE 16 288 -64 288 WIRE 144 288 144 256 WIRE 144 288 16 288 WIRE 352 288 352 240 WIRE 352 288 144 288 WIRE 448 288 448 224 WIRE 448 288 352 288 WIRE 144 336 144 288 FLAG 144 336 0 SYMBOL res 192 176 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 0 56 VBottom 2 SYMATTR InstName R1 SYMATTR Value 10 SYMBOL res 336 144 R0 SYMATTR InstName R2 SYMATTR Value 200 SYMBOL res 192 48 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 0 56 VBottom 2 SYMATTR InstName R3 SYMATTR Value 1k SYMBOL res -16 48 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 0 56 VBottom 2 SYMATTR InstName R4 SYMATTR Value 8k SYMBOL res -48 144 M0 SYMATTR InstName R5 SYMATTR Value 1k SYMBOL cap 128 64 R0 SYMATTR InstName C1

SYMBOL cap 432 160 R0 SYMATTR InstName C2

SYMBOL voltage 144 160 R0 WINDOW 123 24 124 Left 2 WINDOW 39 24 152 Left 2 SYMATTR Value2 AC 1 SYMATTR SpiceLine Rser=10 Cpar=10p SYMATTR InstName V1 SYMATTR Value "" SYMBOL cap 0 160 R0 SYMATTR InstName C3 SYMATTR Value 20p TEXT -96 312 Left 2 !.ac dec 100 10 100k

Version 4 SHEET 1 880 680 WIRE 0 32 -64 32 WIRE 144 32 80 32 WIRE 208 32 144 32 WIRE 448 32 288 32 WIRE 144 64 144 32 WIRE -64 128 -64 32 WIRE 16 128 -64 128 WIRE -64 160 -64 128 WIRE 16 160 16 128 WIRE 144 160 144 128 WIRE 208 160 144 160 WIRE 352 160 288 160 WIRE 448 160 448 32 WIRE 448 160 352 160 WIRE 144 176 144 160 WIRE -64 288 -64 240 WIRE 16 288 16 224 WIRE 16 288 -64 288 WIRE 144 288 144 256 WIRE 144 288 16 288 WIRE 352 288 352 240 WIRE 352 288 144 288 WIRE 448 288 448 224 WIRE 448 288 352 288 WIRE 144 336 144 288 FLAG 144 336 0 SYMBOL res 192 176 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 0 56 VBottom 2 SYMATTR InstName R1 SYMATTR Value 10 SYMBOL res 336 144 R0 SYMATTR InstName R2 SYMATTR Value 200 SYMBOL res 192 48 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 0 56 VBottom 2 SYMATTR InstName R3 SYMATTR Value 1k SYMBOL res -16 48 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 0 56 VBottom 2 SYMATTR InstName R4 SYMATTR Value 8k SYMBOL res -48 144 M0 SYMATTR InstName R5 SYMATTR Value 1k SYMBOL cap 128 64 R0 SYMATTR InstName C1

SYMBOL cap 432 160 R0 SYMATTR InstName C2

SYMBOL voltage 144 160 R0 WINDOW 123 24 124 Left 2 WINDOW 39 24 152 Left 2 SYMATTR Value2 AC 1 SYMATTR SpiceLine Rser=10 Cpar=10p SYMATTR InstName V1 SYMATTR Value "" SYMBOL cap 0 160 R0 SYMATTR InstName C3 SYMATTR Value 20p TEXT -96 312 Left 2 !.ac dec 100 10 100k

I hope it works better than this f$%$#@%* simulation which defies you to make anything work.