Making an engineering evaluation isn't rocket science--find out where it stops oscillating and then swamp it some more for a safety factor. (The impedances can change with output current, of course.)
Cheers
Phil Hobbs
Making an engineering evaluation isn't rocket science--find out where it stops oscillating and then swamp it some more for a safety factor. (The impedances can change with output current, of course.)
Cheers
Phil Hobbs
There are cases where a big fast load step makes it ring slew-rate limited, a dying sawtooth. Slew rate is a sort of bandwidth reduction; I think that's what's called a limit-cycle oscillation. The 1 uF case does that pretty obviously.
My loads on the split rail are actually tiny, basically biasing up some diffamps. But this instrument has real 16-bit resolution, or sometimes more, and a little crosstalk between channels might be noticed.
That I believe. I sort of suspect that it's the output current limit rather than the slew rate, but if it's some fancy-schmance architecture the SR might be set by something other than the pole-splitting cap and the tail current source on the input pair.
Cheers
Phil Hobbs
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