I am loathe to admit my ignorance in a public forum, but I have gone over this change and do not understand how it will work when you switch the enable and clock pins. If I had the parts in-hand, I would breadboard it and learn it that way, but they won't be here till the end of the week. I am staring at the data sheet and not seeing how the
4017 will get clocked at all using this method.
Would you mind taking a minute and explaining how that last stage, the
4017, will get clocked correctly with these changes? Thanks for your consideration, and your patience.
The 4017 has two clock related inputs: CP and /CE. You have two options when using these: 1) apply clock to CP and use /CE as clock enable, which means when /CE is held LOW, the counter increments on a positive going edge of clock signal applied to CP, and this is inhibited when /CE is HIGH; or, 2) which is the opposite, apply clock signal to /CE and use CP as clock enable, which means when CP is held HIGH, the counter increments on negative going edge of signal applied to /CE, and this is inhibited when CP is LOW. The 4060's are negative edge triggered counters, so you want the 4017 to be negative edge triggered too. Therefore option 2) is appropriate. See the "truth table" on page 2 in the datasheet:
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or on page 2/11 for the "mature" family here:
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. They are functionally the same regardless of family- they may be calling /CE CLOCK INHIBIT, it is all the same. Also, you could rearrange the circuit like so with double Tosc period, note that I am using Q1-Q14 notation for the 4060's , and Q0-Q9 notation for the 4017- this just happens to be the way the datasheets do it so get used to it. Also, the datasheets are not consistent with the notation for the RS input-also calling it phi 1 or something- it is the input to that leftmost NAND gate in the logic diagram:
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