non-pipelined fast ADC

This makes no sense; if you lock it to the XO with any variant of phase-locking, it's NO LONGER phase-locked to the trigger event, and the measurement is worthless. Just cancel the trigger-caused start phase against an XO-caused start phase, and ignore the absolute frequency of the LC entirely (unless you think it drifts enough in a few milliseconds to matter).

You've never actually used a state-of-the-art digital delay generator, I gather. Good ones have jitter down around 10 ps over fairly long periods. Even the SRS DG535 I bought ~25 years ago had jitter less than

The idea that an LC oscillator could hold the necessary phase accuracy for milliseconds is ridiculous.

Cheers

Phil Hobbs

The LH0033 and LH0063. I asked Bob Pease why their 1990 databook changed it to "fast and very fast", and he said the edict came right from Charlie Sporck.

Cheers

Phil Hobbs

Most of the older HP analysers drifted a lot and needed a warmup period of anything up to an hour before they were fit to use. Both the 8566 and

Have one of each here, came from an rf / emc lab amd must have been on

Chris

And getting harder. The SDR-based analyzers are so cheap that they're taking over the market.

Cheers

Phil "YIG-tuned forever" Hobbs

I did one OEM delay generator that used an unlocked, triggered coaxial ceramic resonator oscillator. It was better than an open-loop LC, but not good enough.

The SRS boxes use the XO to count out time delays. But in the front-end, they measure the delta-T between the external trigger and the local XO clock, and then subtract that out of the back-end pulses. It works sort of OK, but their boxes are user-interface horrors. The DG645 was designed by a guy that I fired.

SRS loves to spell out messages in 7-segment. I always thought it would be fun to write a novel in 7-seg text.

The French thing apparently uses SERDES blocks in an FPGA. I think the idea is to just run the digital counter stuff really fast. RMS jitter is clock period divided by the square root of 12, which seems magical to me.

We'll have a new DDG soon.

Isn't a YIG frequency determined by the mag field? How can that be controlled to PPB precision?

The od HP5359a time synthesiser of similar vintage, should do that as well...

Chris

IT UAS A OARK And 5TOrnn4 nI6HT....

That's the normal RMS uncertainty of an ideal digitizer.

Looking forward to seeing it!

Cheers

Phil Hobbs

Seems like it was 100 ps typical vs ~10 ps guaranteed for a modern one, and only over a much shorter delay.

Making a really good DDG is a hard problem, for sure. I've never built one myself, but I've happily used several, mostly SRS.

In my current incarnation I have a Highland P400, which is my go-to pulse generator for most quickish things. Right now I'm working on a POC for a bathymetric lidar, which will use the P400 and some coax cables to clock a dozen or so fast T/Hs at different delays.

Good medicine.

Cheers

Phil Hobbs

It has a super-high Q and a narrow control bandwidth. SDRs have all sorts of sample clock jitter that a DBM driven from a YIG-tuned oscillator avoids. The difference is 30-50 dB close-in phase noise, nothing subtle at all, at all.

Cheers

Phil Hobbs

There's no milliseconds required on phase accuracy; that's only for the LC frequency drift from a measurement cycle to a subsequent calibration cycle. It's not necessary for the LC to give an accurate sine, just a repeatable waveform, and any jitter is irrelevant except as an addition to the thermal-noise contribution.

Just start a ramp and stop it on the next clock edge - actually the next cl ock edge but one to make sure that the ramp has been ramping long enough th at initial transients have gone away, then digitise where the ramp has got to.

Digitising a sine wave and the complementary cosine wave would have worked just as well.

Two ADCs would have been more expensive than our ramp generating circuit (w hich was just a couple of 5GHz broad-band transistors) but it is certainly a more elegant solution.

The cosine wave wouldn't have to be exactly complementary if you kept track of the actual phase difference from the notionally in-quadrature waveforms (which wouldn't be difficult).

The start a ramp and stop it approach what we did back in 1988. There was a lot of auto-calibration - which got repeated every few minutes - to make sure that the ramp voltage we digitised started at the bottom of the range of the ADC we were using and always stopped just before the top of the rang e.

We used slow DACs to set the starting point of the ramp and and the current charging the capaictor.

Having pairs of delay board with a built-in delay generator made this prett y straight-forward (compared with some of the other stuff we were doing).

I spent a lot of time talking to the guys who wrote the software that made the system work, but I didn't have to discuss that bit - it all worked. I'm sure that there were holes in my original specification, but the guy that implemented the system was really good (and found that aspect of the desig n tricky enough to be interesting), and the guy who took over after he went away was pretty good and very thorough (and - very nominally - my boss fro m then to the end of the project).

As the wise man said, "When you find yourself in a hole, stop digging." ;)

Reiterating point 1: you've obviously never used a state-of-the-art DDG, at least not at a level where you needed to knew what it did.

An accurate, repeatable, low-jitter delay on an asynchronous waveform is what a DDG is all about. See point 1.

How would you estimate the thermal noise contribution exactly?

Cheers

Phil Hobbs

But this is about a triggered LC generator, not about a delay. Why would a digital delay generator be involved?

Minimize, not estimate; you have to buffer the LC waveform into an ADC, and that means the buffer amp has some high input impedance, and presumably introduces its own noise (or if you lower the input Z, pulls the LC amplitude or frequency).

A pretty good triggered LC oscillator will pile up jitter at very roughly 1 picosecond RMS per microsecond. The junk it takes to start and stop it compromise the Q some. So it's good to close the PLL and lock it to a crystal within a microsecond or two.

A cheap XO will have jitter of maybe 20 ns RMS per second, less if you get a good one by accident. A $70 OCXO will be roughly a thousand times better.

The XO or OCXO will improve greatly with a cover to keep air currents from wafting over it.

Sure it can!

In single-sweep mode at least...

-- john, KE5FX

On a sunny day (Sun, 30 Aug 2020 14:08:38 -0700 (PDT)) it happened whit3rd wrote in :

Indeed. Perhaps if you PLL the LC to a precision reference and set its frequency via a DAC and varicap, that would be like tuning a tuning fork by removing or adding some weight as in the mechanical equivalent, and then leave it (maybe do that calibration just before the measurement, calibration button?, Trigger would be like pinging a precisely tuned crystal / tuning fork. The tuning needs not happen _during_ the trigger, assuming drift is OK?

Anyways he also writes mF (milli Farad) if he means uF (micro Farad) I think, so .. factor a couple of thousand, so maybe it is not so critical ;-)

I'm a happy user of your GPIB Tools via a Prologix GPIB-Ethernet adapter. Thanks for making them available!

Cheers

Phil Hobbs