non-pipelined fast ADC

Am 26.08.20 um 15:26 schrieb Lasse Langwadt Christensen:

The first thing i had to build after grad. was a signal averager with a 8 bit 20 MHz flash converter. We got one from the TRW salesdroid in an clear epoxy cube. You could see the reference ladder on the chip with bare eyes. It took 8 74LS computation units in parallel/round robin to do the averaging.

(really the boards in the background. On top is the first fpga implementation. There was an intermediate 100K-ECL version for 200 MHz.) The TRW flash ADC is the large chip on the bottom-right.

DK, too

When one clock delay at 100 MHz is OK, so are

Cheers, Gerhard

You can make time-to-digital converter by using a fast ADC to digitize a ramp or maybe some other waveform. The ADC is clocked by your local XO, and the ramp is started by some external event. The ADC samples can be processed to tell when the event started, measured in the local time frame. That's one way to answer the question "when was this box triggered?"

It's a hobby. I did a couple of products with triggered delay-line oscillators, specifically coaxial ceramic resonators, but LC is better. HP did some nice boxes, like the 5370 time-interval counter, with delay-line oscillators. The 5370 manual is worth reading.

HP made one delay generator box that did kick-start an XO when a trigger arrived. It was a nightmare and didn't last long. An XO is hard to start and hard to stop.

I met a guy who worked on it. He was scarred for life.

Right. It's a nice example of the "initial conditions" concept of differential equations. If you record all the voltages and currents of a circuit, you can restore them later, and it takes off as if time had been suspended. You can pause a Spice simulation, same idea.

I'm just revisiting all the ways to make a DDG. New parts and new ideas happen. So do competitors. If I discover anything, I'll add it to the Wikipedia article.

And SED should discuss electronics now and then.

HP sort of did that. They ran a delay-line oscillator all the time, and phase-locked it to an XO. That kept it stable when not otherwise being used. When they got a trigger, a one-shot quenched it for 75 ns, then kicked it off again. Then a clever heterodyne system phase-locked it again, but preserved the original trigger time frame. This was done before fast ADCs and fast DACs existed.

I did one product that used an XO, but rotated the phase just after trigger. It worked but was too tricky. Pepper's interrupted ramp idea is brilliant but is also tricky to implement.

That's not a lot of time, at 800 MHz.

The older high end HP spectrum analysers, the 8566 and 8568 did that as well. The marketing blurb called it lock and roll, locking the LO at start of sweep, then free running it open loop for the rest of the sweep. Allowed them to have a stable 10Hz resolution bw and

I think what I was really saying was, was if the solution gets too complex, it maybe the wrong approach :-)...

Am 26.08.20 um 18:29 schrieb Chris:

IIRC, there was an article in the HP Journal about this. I think I have it on paper somewhere, but HP Journal is probably searchable somewhere.

Cheers, Gerhard

This one?

piglet

I think i've seen that.Amazing bit of kit for it's time. HP really were at the peak of their game back then with tech prowess few, if any could match. Much of it still in use today.

Last catalog price for the 8566, iirc, was 78,000 usd and yet, they sold bucketloads of them...

onsdag den 26. august 2020 kl. 17.03.38 UTC+2 skrev snipped-for-privacy@highlandsniptechnology.com:

yeh and you probably have to keep up the clock rate anyway to not lose all the gain in processing

as an example maxim also have dual 6 bit 90Mhz with 1 cycle pipeline, but looking at the datasheet it is more like one cycle for sampling, one cycle to the pins and then you need another cycle to get it into an fpga

Why not turn it around, and trigger the ADC with the external trigger signal, and make it take a sample of a RF sinewave locked to a crystal. Another ADC can take a sample of a RF cosine wave, and you can compute the trigger time. You won't need a fast ADC, just one with a fast sampling bandwidth which is a lot easier.

If you need to resolve ambiguity about which cycle you got, you can also sample some slower waveforms too, which could be more sinewaves or digital. You might not need ADCs for those ones, e.g. you could latch the output of a gray-code counter, perhaps all of that in an FPGA.

But, the HP trick used tuned delayline oscillator frequency only because they were using a one-bit (latch) detector with their master oscillator clocking it, to detect the triggered oscillator phase. It had to be part-per-thousand locked to the master oscillator frequency to generate the phase-decode-event, with that one-bit detector, using (basically) one thousand one-bit detections to generate 10 useful bits of information.

Your triggered LC doesn't have to match the master oscillator; all it has to do, is generate a sequence of events (or ADC samples) after the trigger event, then make a second trigger event with your master oscillator, and compare the ADC outputs for the phase shift... with some FFT capability, that works out totally independent of the LC frequency (except for the small delay - a few milliseconds?- between the two event/convert cycles). Instead of a thousand samples, you can do four-bit conversions on

Yeah, and damping the crystal to a halt between event captures is a BIG problem; damping a delay line is a problem. Damping an LC can be complete in under one cycle time, hardly any problem at all.

That has been done, but the cheap and fast ADCs are pipeline types that need a continuous clock.

And one ADC sampling one signal in that direction will have time ambiguities.

Right. You'd need two ADCs to resolve the ambiguity.

That's all pretty complex. One ramp and one ADC works.

Not all that well. When I had to deal with the problem back around 1988, we used a fairly stable fast clock running at 800MHz (locked to a 50Mhz crys tal clock), and detected the leading edge of the interval to be timed, samp led the digital output of the long synchronous counter keeping track of the oscillator output, and measured the time to the next clock transition by s tarting a ramp, stopping it on the next clock transition and digitising whe re the ramp had got to. We did the same thing for the trailing end of the interval. The granularity should have been 5psec (which wouldn't have been bad at the time) but we had to settle for 10psec to get around a problem t hat would have been fixable if we'd had more time. There was a 60psec jitte r on the clock edge we were counting - we need a better 800MHz clock and co uld have got it by spending money which we would have got if the project ha d gone into production (which it didn't).

It worked fine. It was somewhat complicated, but the whole project - a stro boscopic electron microscope for looking a voltage change on the surface of working integrated circuit chips - was intrinsically complicated.

Back in 1982, when I was working in satcom, we had a reasonably new Ailtech 757 (iirc). It was a manually-tuned gizmo that drifted around a bit before it warmed up.

Then we got a swoopy new HP 8566A, later upgraded to a B. I was hooked. I had one for awhile at IBM, and about 6 years I bought a used one on eBay when I needed more top end than my previous 8568B. Its close-in phase noise is remarkably low on account of its YIG-tuned sweep oscillator.

Its main drawback is that you can have the RF or microwave band displayed, but not both at once. Still, for 2 cents on the dollar one really can't complain too loudly. ;)

Cheers

Phil Hobbs

Just rereading this thread. How about sampling the XO when the trigger appears, at the same time starting the LC. If you know which half-cycle the XO is on (which isn't too hard to do) you can compute the I/Q coefficients that make the initial phases of the LC and XO match. (For extra credit, two XOs locked in quadrature would allow you to always be on a good part of the slope, as well as disambiguating the quadrants.)

That would work better in a DPLL, I expect.

Cheers

Phil Hobbs

I'm thinking along those same lines. If I can (quickly!) measure the phase angle between my XO and my triggered oscillator, I can seize the initial phase offset and close a loop on that. I did that a long time ago with all analog parts, but it was ugly... think compound sample-and-hold horrors. Rethinking it mostly digital, it looks interesting. Rather not say more in public.

My triggered LC oscillator is great for a couple of microseconds, but is piling up drift and jitter. It needs to be locked to a good XO long-term.

It would *only* work if your PLL regime was rock solid. I've been out of it for a while, but if timing of the digital waveforms I've dealt with got smashed by ... things, you'd have to completely reaquire any nodes subject to it.

I wrote the state machines for the analog and DPLLs ( why not both ?:) for the base station. It wasn't straightforward. And in my faulty recollection, it mainly just got nodes back online faster.

Hopefully that was all just noise, which would be lower in this use case.

Sigma-C is a thing...