You don' thave the latch in the library (which I suspected). It appears that it's not smart enough to make one out of gates. Synplify would, but bitch like hell doing it. There is a difference in tools.
Look at you IOBs. You may have an IOB that has an implied inversion. The Xilinx IOBs were a littttle crazy with OE's, it wouldn't surprise me that Altera had similar nonsense.
:D
Its amasing just how many pins some of theses devices have, and with oudles of gates too and 400mhz clock speed etc, and yet they stil dont consume that much more power than some of the small ones.
Im realy tempted to try and do something neat to do with all those pins but cant think of anything right now.
Yes its easy to verify setup times are met with clocked logic as everything just adds up between the edges.
Metastable states in asynch loops can cuase nightmares but they still have defineable boundries, the latches in the macro cells have internal async loops hence the setup and min clock width timings inorder to avoid metastable states but it is much more controled as they will only have 2 adjacent virtualy unloaded gates in the loop.
In logic wich has numerous feedback loops all the possible circular paths can be very complex and hard to ensure metastable (or race conditon) states are avoided, but as the theory is reasonably simple a computer should be able to handle the complexity, but it seems the tools are made to do it the easy way.
However it seems high speed clocks accross large chips are cuasing problems and theres interest in using more asycnhrounous techniques such as mixed non synchronised clock systems however these seem to cuase as much problems, if you could make a microprocessor internaly completly asynchronous (with of course suitablly generated handshaking for every movement of data) it would avoid clock issues altogether.
ah yes of course, il have a look to see if there are any asycnhrounous sr latches already there.
That reminds me of trying to use high level languages in multi tasking embeded systems.
Colin =^.^=
I tried this, it cleverly sees theres a SR latch here and goes ahead and uses one but then gives an error :- 'xxx devices do not have latch with both async set and reset. Fitter may fail' (wich it does)
Il gues il stick to schematic entry as this seems to work although I still havnt figured out how to stop it using negative logic on the outputs with some devices.
Colin =^.^=
Thanks, I'm using Lattice as Altera doesnt seem to do the small parts, it seems to use the synplify compiler for vhdl, but im just using the schematic input method now as that seems to produce a fit in the small parts ok.
Ive looked at the IOB on the data sheet and although they have inverted outputs there is an xor with one input set high or low wich shld enable selection of active low or active high outputs, both the 16v8 and 22v10 have inverted outputs with an xor stage and one comes out inverted (q apears as !q next to the relavent pin on the generated pinout diagram) the other doesnt, im not sure if I should acount for that in my equations or not. i think i might be able to figure it out from the jedec file, heck il probaly end up just writing the jedec file.
Ive looked through the help files however many of the menus/icons I tried to folow are greyed out wich probably means i need to go and look for more modules to instal or something. it says something about a constraint editor but the only option i have is to import a constraint file not edit it.
Colin =^.^=
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