Yes, that basically enables the global interrupt system. It's usually coded in the assembler as EINT. But it's just another name for BIS #8, R2.
BIS is a double-operand instruction formatted like this:
1 1 0 1 Sr Sr Sr Sr Ad BW As As Dr Dr Dr Dr
The first bits, 0xD, specify the BIS instruction. The next four and last four specify the source and destination registers. The Ad is the destination mode, the As pair is the source mode, and the BW is the byte/word mode.
The EINT is coded up as 0xD232. This basically means:
BIS SOURCE=R2 in mode 3, DEST=R2 in mode 0
The MSP430 supports four source modes and two destination modes. Four source modes are _register direct_, _register indirect_, _autoinc indirect_, and _indexed indirect_. Two destination modes are _register direct_ and _indexed indirect_.
However, R2 (and R3) is special. If you use it as a source or destination register in _register direct_ mode, then you get the status register. However, if you use it as a source register in any of the other three modes, you get a constant generator value (it ignores the usual meaning and decides to grab from hard-wired values.) In source mode 3, R2 is taken as a fixed constant 8. However, the CPU4 bug present on some of the processors causes this not to work. Which is why one might choose to use a special macro, so that it can be adjusted based upon the actual target. The BIS #8, R2 won't always work on every MSP430, memory serving.
Just as a side note, using R2 as a destination register in the other mode, _indexed indirect_, causes the processor to instead use _absolute mode_ (basically, _indexed ZERO_ mode.) Had that been the case, the absolute address would have followed the instruction and the BIS #8 would have applied there.