This may be a generic query to PICs, I'm not into that series enough to be sure. Anyway, here goes:
Page 64, section 9.5 of the datasheet for the 12F675 refers to saving the state of the processor prior to processing an interrupt. It describes how to save the W and status registers, and in paraphrased form:
"The user register W_TEMP (used to store W) must be defned in both banks, and both definitions must be at the same offset from the bank base address...."
Given that the address field for data instructions with this processor is only 7 bits, I can't see what this means in practice, given that bank 1 starts aat 0x80. Also, I can't see any syntactical way of achieving it without incurring multiply defined errors. My PIC handbook is no help. Can anyone shed any light? TIA
Right, that's absolutely correct. When an interrupt occurs, and the ISR is entered, the ISR doesn't know which bank is currently selected. IOW, RP0 and RP1 are unknown upon entry to the ISR. The catch is that you can't check to see which bank is selected until you save the current context because checking destroys the context. Therefore, you need to be able to plunk down the context info in some manner that doesn't depend upon which bank is selected. Fortunately, most PICs have some amount of RAM that is mapped into all banks. The 12F675 only implements bank 0 and bank 1, and ALL the RAM is mirrored in either bank. IOW,
0x20 & 0xA0 are the same location and 0x21 & 0xA1 are the same as well. Accessing either location will produce the same data.
You are correct in that the op-codes generated will only have 7 bit offsets, but they will be extended by prefixing them with RP0 and RP1. Note: RP1 is a moot issue on the 12F675. If you have been able to successfully initialize your chip, you already know about RP0 (unless you're using the BANKSEL macros ;-)
As far as usable RAM goes, you really don't have to worry about it on the 12F675. It is good to know how this works though. BTW, don't forget to save/restore FSR and PCLATH if applicable to you.
The following code is from another PIC, but it should work for you as is.
To define some storage:
cblock 0x20 ; ; ISR Register Save Areas ; W_TEMP STATUS_TEMP FSR_TEMP PCLATH_TEMP endc
To save everything:
org 0x004 ; Interrupt handler right here movwf W_TEMP ;Save everything swapf STATUS, W movwf STATUS_TEMP movfw FSR movwf FSR_TEMP movfw PCLATH movwf PCLATH_TEMP
bcf STATUS, RP0 ;Make sure we are in Bank
To restore everything:
; Restore everything and return IntExit movfw PCLATH_TEMP movwf PCLATH movfw FSR_TEMP movwf FSR swapf STATUS_TEMP, W movwf STATUS swapf W_TEMP, F swapf W_TEMP, W retfie
Check out the Midrange reference manual (DS31008A) section 8.5.
The crux of the matter is that (in general) the current bank is not known at the time it is necessary to save the W register (upon first entering the ISR).
However, as this micro only has two banks and the addresses 0x20 to
0x5F in bank 1 just access bank 0 anyway, it doesn't really mean much in this specific case. It does mean something in 14-bit instruction PICs where there are unique general-purpose registers (not just SFRs) in each bank.
Note also the use of the SWAPF instruction.
(If you were to implement nested interrupts, you'd obviously have to move the saved W register somewhere else before re-enabling interrupts.)
Best regards, Spehro Pefhany
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