MOSPOWER DC Loop

Happy Holidays SED :)

I'm driving the first circuit frag below with an emitter follower, simplified and shown in the second frag.

I've tentatively plonked down IRF530 & IRF9530 with +/- 40 VDC rails. Currents shown are approximate - there's a small imbalance effecting a 50 uV output offset, closed loop.

What range of DC offset errors are typical in a power amp? I don't recall ever seeing this spec listed. I found:

Less than 100mV (< 20 mV typical **):

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and "I always have less than 30mV (and usually less than 20mV) DC offset at the output." at:

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That gives me a warm fuzzy feeling. Maybe there's nothing to this - let's see.

My input is modeled as a DC offset in series with the feedback VCVS.

I put an AC signal on this thing in open loop and the output follows nicely in transient analysis.

I ran DC operating point in Spice.

I would think that merely lowering the level at the base of the emitter follower by the offset would do the job, but that's not happening. The VCVS gain is -10,000. -1000 results in a 500 uV offset. So I'm looking at a required DC gain of 10,000 to get 50 uV offset - not astronomical, but I didn't expect that. 5.4 mV offset with VCVS gain = -100 hmmm...

Seems that something is messing things up like maybe the MOSFETs operating at this low Vgs need a little more push to get the offset down, perhaps exacerbated by the action of the Vbe multiplier. I'd prefer a way to pin the output locally without all that gain.

What do you think?

| | | | V | I | b +------+ | | | |

1.2 mA | | | .-. | | | | | ||-+ 5.4k | | | || 70 mA| | | | | | | | | .-. .-. +------||-+ | | | | | ||-> | | 8 600 | | | ||-+ '-' '-' | | | | | | | | | | === +------+ | GND | | |

V+ --- | | R | |/ +---------| | |>

| | .-. +------- ( + ) | Gate ( ) .-. ( - ) ( + ) out 55 uV '-' ( ) ---+------+ | ( - ) Vbe Mult | | | '-' | | +----o .-. | Gate | | |Av = -10000 ( + ) +------- | .-. | ---> ( ) | | | | | ( - ) .-. 9.2 mA | | | 8 | o VCVS '-' ( | ) | '-' .-. | | ( | ) | | | | === === ( V ) | | | | GND V- '-' | === '-' | | GND | === | | V- | | | +----------------------------------------------+

created by Andy´s ASCII-Circuit v1.22.310103 Beta

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Best Regards,
Mike
Reply to
Active8
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You should be aware that spice models of most all power MOSFETs are practically useless for the analysis you hope to make, because they fail to model the FET's subthreshold region that's all-important for linear power-amplifier design. Any MOSFET meant for serious power- amplifier use must have a large die area for adequate heat removal, which means you'll be operating it at a low current density, i.e. a low current compared to its capability, and therefore well into the subthreshold region not covered by most power MOSFET spice models.** I've written about this sad scene here in s.e.d., illustrating with real data. A second serious problem is the MOSFET's Vgs temperature drift, which changes dynamically throughout the signal swing. This effect is especially significant at low audio frequencies, yet it's completely ignored by power MOSFET models available to most of us.

The bottom line, spice analysis of class-A and class-AB MOSFET bias circuits usually cannot be relied upon, and therefore can't properly be the basis for any "warm fuzzy feelings." I'm sorry about that!

You can read Cyril Bateman's four articles in Electronics World (Oct, 2004 to Jan, 2005) to get some idea of the spice-model modifications required to address these issues.

** An exception may be models for some lateral power MOSFETs. These FETs, such as those made by Hitachi, have negative Id vs Vgs tempco at their typical operating currents, and are therefore better suited for use in audio power amplifiers.
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 Thanks,
    - Win
Reply to
Winfield Hill

The part about ineffectively flogging Spice is correct. But as it happens you'll probably find the models in Cyril Bateman's articles to be rather intimidating. So I suggest dropping the spice models.

My true AoE-style approach is to use analytic back-of-the envelope calculations, to find out what parts of the design are troublesome. Here we need to explore the FET's subthreshold region, and its Vgs temperature drift. If we get that far successfully, we can examine the dynamic signal-swing aspects.

It's a rather big area to explore, but we can touch on the subject. Let's consider the IRF530 and IRF9530 FETs you selected (BTW, these are rather wimpy parts, rated at only 88W with 25C case temperature, much less with hot heat sinks and 0.5C/W insulating pads).

First, let's pick a class-AB bias current. If we choose 150mA with +/-40V rails, that'll be a 6W standby heat dissipation for each FET. Examining the IRF530 datasheet's Typical Transfer Characteristics plot, we see that roughly 4V of gate-source voltage will produce 150mA if the FET die is at 25C. From the slope of the curve we can estimate the current will increase by 100mA for a gate-voltage increase of 50 to 100mV. We also know there can be more than a volt of gate-voltage variation from FET to FET, so if we were to set the gate voltage for a "typical" FET and then change parts, we could be in big trouble, with bias currents of 30x or 1/30 of what we expected.

Next we can examine the situation for a hot die, at the maximum rated 175C. The curves show that a typical 4V gate bias that set 150mA of current at 25C will cause over 1A at 175C, which is a very bad scene indeed. Unfortunately these curves don't show us the typical gate voltage for 150mA, but it could be about 2.5 to 3V, which is a very big change from the situation for our cool FET junction. If we set the bias voltage at 2.5V, to handle the case of 175C maximum junction temperature, then the output stage class-AB operating current at 25C would be 0mA, which means we'd suffer from high crossover distortion. We could drop 1.5V at 150mA across a source resistor, but that'd be a 10-ohm resistor, which would waste more power than the load!

BTW, note the zero tempco gate-voltage for the IRF530, with its high 7.5A drain current. With 40V rails and 7.5A bias you'd have to run the FETs at 300W to take advantage of this zero-tempco point. :>(

These issues are the motivation behind LTC's LT1166 MOSFET bias chip, which lets you use common cheap power MOSFETs in audio amplifiers.

Don't forget my other suggestion: check out Hitachi's (now Renesas) lateral power MOSFETs, which have nearly zero gate-voltage tempcos at sensible drain currents.

--
 Thanks,
    - Win
Reply to
Winfield Hill

It's a small internet. That's a good idea - testing the spkrs. I hope they're all close, though. Don't need a spkr dependant amp.

It looks like unless I purchase those papers Win mentioned, I can flog Spice all day long and get nowhere.

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Best Regards,
Mike
Reply to
Active8

There's the idea of putting small DC voltages into various woofers, and checking how much voltage causes visible movement of the cone (thus "biasing" it so it has less distance to bottom out in that direction, lowering the max available volume). Also, measure the DC resistance of these woofers, and calaculate how much power the voice coil will dissipate with just the DC voltage on it. Not only will the DC power be higher than the same value of AC voltage (the 'impedance' is lowest at DC), but the voice coil is SITTING STILL with DC on it, as opposed to being moved through the air with an audio signal. I've never heard of a DC power rating for a speaker, but no doubt it's a lot lower than its audio power rating. These should get you some decent 'better not go above' limits.

I have a mostly-unrelated comment about that webpage, c "The circuit for the bias servo (actually the whole amp, with some of the other mods I have mentioned elsewhere) is shown in Figure 1a - notice that I left the diodes in circuit as a fail-safe, since the servo I used will go open circuit if the pot wiper becomes disconnected (I strongly suggest that you do the same)."

The pot with wiper to the base bothered me, because I recalled reading about the possibility of the wiper opening up and causing Bad Things to happen. I looked ii up, and it turns out it's by the same author, on this other page:

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Reply to
Ben Bradley

I can probably deal with it up to the point that it's useful, but I'm counting on the control loop to take care of that which I can't see/foresee.

That chip was interesting to read. It's a nice little control system.

0.5 Vgs 100 mA Id and below. That pretty much solves that problem.

I knew those [9]530s weren't the thing to use. It was convienient to drop the subckt in just to examine methods of controlling things. Despite the potentially crappy model for this purpose, I've demonstrated that I can control the idle current and the offset. It's more effort at control than any MOSFET amps I've found on the web. Notice there isn't much of that and even less in the way of audio MOSPOWER parts. Seems like everything is geared to class D now. Even the VMOS guides I found from the '80's only touch on audio apps. The things just weren't designed for that.

Thanks for shedding some light on the preblem.

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Best Regards,
Mike
Reply to
Active8

Have to to keep an idle current running. Couple of fractions of mV error throws it off.

Haven't seen that done yet.

Notice the circuit at the beginning of this thread isn't much different. I set the current through R1 and R2 (which in my circuit is a Vbe multiplier) and thus the Vgs according to MOSFET idle current sensed at the drain. The output is servo'd close to zero so the idle currents are equal. With the current thru the Vbe mult holding Vgs steady, that branch can be driven with a bjt follower.

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Best Regards,
Mike
Reply to
Active8

For HEXFETs it might be useful to consider a scheme that biasses the MOSFETs at just below Vgs(threshold) and have a Class A(B) driver stage with enough current capability to supply the crossover load current itself.

Something that might even take advantage of the need to bias the MOSFET Vgs at about 2V.

+------------+--- V+ +AC | | | |/ | +---|npn | _|_ |e |--+d D1_/ +--------||N | | |--+s | [R1] | | | | [R3] +------------+----[Rload]--- 0v | | | | [R2] | _|_ | |--+s D2_/ +--------||P | |/e |--+d +---|pnp | | | | -AC | | +------------+--- V-

The two transistors would be a TO-220 pnp/npn pair, dissipating about 5-10W?, so mounted on the heatsink.

R1/R2 would be a relatively low value, say 50 ohms as a first guess, with about 2V across each. So R3 would be about 1k, with 4mA bias current through it. The bipolar AC drive assumes active pull up/down driving, as per the recent thread(s) on taking the outputs from the supply rails of an opamp.

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Tony Williams.
Reply to
Tony Williams

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