Hello all,
Lately, I've been going over esd protection schemes. Many ESD protection are referred to as *snap* type or *snapback*. Looking into the snapback caracteristics of a MOS device, I found myself extremely confused. (There a very helpful thesis link for this topic which I obtained by an earlier post. I forgot which post).
This is the snapack I-V of NMOS (view in fixed font):
(Ids) / / / / / -----------
=A0(Vds)
Are you assuming that the ESD event occurs when there is a power supply also connected to the pin? Otherwise it is pretty clear how the current and hence voltage will return to zero after the ESD, when the stored energy has all been dissipated.
In general (perhaps unlike equipment) chips themselves are not ESD tested with any power supplies attached, so the chip vendors will not see the problem of the ESD cell staying latched on, even if it really could occur in an application. (Separate latch-up testing is done, but the peak current is much lower in those tests.) I have even heard of SCRs used for ESD protection of power rails, which allows good robustness when the device is ESD tested without power supplies attached, but which might be entertaining if there is a low-resistance battery attached (using leads with some inductance so that the ESD voltage can still trigger the SCR).
Regarding the drain voltage being too high for the device during the ESD event, I think that the snapback is not triggered by oxide breakdown but more like some kind of parasitic bipolar device caused by the drain and source n-type diffusions and the p-type substrate between them. I think that some method of biasing up the gate from the ESD pulse is sometimes used, and somehow this helps the snapback to start, but I don't know.
Certainly the voltage on the drain can still reach values that could damage the gates of small FETs connected to those pins, and it is normal to interpose secondary ESD protection consisting of some series resistance and smaller clamp diodes or similar wherever this does not reduce the circuit performance too much. The secondary ESD protection does not have to be made of such big devices because the current has mostly been diverted by the main ESD cell.
You could probably find out quite a lot about ESD protection by reading patents because all of the most obvious solutions have been patented by now, and for many companies, the choice of which structure to use is probably dictated by avoiding the remaining un-expired patents.
Chris
Hello,
Thank you for your reply.
What concerns me is that snapback will begin at voltage that exceeds the oxide breakdown voltage. Like you mentioned, snapback is caused by the parasitic bipolar device of the nmos and does not seem depend on the oxide breakdown. This is why (from an ESD-novice point of view) a classic clamping mechanism to the power rails seems to be offering a more reliable protection to the mos gates - even though it limits the input voltage range to -0.5V to Vcc+0.5V. But I must be missing something otherwise these ESD snapback ccts would not be used,
-Roger
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