More ESD-diode leakage paranoia!

Yeah, ESD diodes are tricky. Unexpected things happen in dual/quad opamps, analog multiplexers, and mixed-signal parts. Unless you're sure it's safe, it's best to never turn on an ESD diode.

The worst thing that can happen is that forward-biasing an ESD diode triggers an SCR latchup that shorts the power supply. Some latchups, like in LM35, don't damage the chip but stop it from working.

Most dual diodes and transistors these days seem to be individual chips, bad thermally but electrically isolated.

Even staid old Darlington arrays have their quirks:

"In normal operation, the diodes on base and collector pins to emitter will be reverse biased. If these diode are forward biased, internal parasitic NPN transistors will draw (a nearly equal) current from other (nearby) device pins."

--sp

Since these effects have been bad news for 40 years or so, I wonder why IC designers keep doing it, and why data sheets are so careful to avoid mentioning it.

CMOS analog multiplexers usually have an apparently similar problem, but it's usually caused by the switch fets turning on, not necessarily the ESD diodes.

The reason is ever the same: cost.

NT

Huh, I never understood why they were all isolated. Thanks.

George H.

IC designers keep doing it because they've got away with it for 40 years Data sheets avoid mentioning it because it isn't tested. It's not tested because then it'd have to go in the data sheet...

Yeah, CMOS (with a few exceptions like SOS) use doped semiconductor for isolation, and the 'reverse bias' just makes the layered structures act like a transistor, and leak when the channel is ON. HV CMOS is especially annoying.

Partly it would be because the parasitic structures are not in the schematics that SPICE simulates, so the designer only finds out about the problem after first silicon at which point there is a strong incentive not to pay for new masks. The LVS (layout vs schematic) checks that the netlist from the schematic matches the connectivity and size of the devices in the layout, and at least some companies do include modelling the diode from the isolation wells to the substrate, but I have never seen anyone model what happens to the carriers once they get into the substrate. Two diodes to substrate get modelled as two diodes, even though they are close enough together to form a transistor.

New designers only find out about these effects when one of their chips fails in an application circuit or in latchup testing (at which point the cheapest fix is some kind of warning in the datasheet), or by listening to the stories from older designers who have made the same mistake earlier.

As far as I know, latchup testing only involves applying currents to the external pins that turn on the ESD diodes. I have seen chips that latch up on other events such as enabling a bandgap reference before enabling the power supply regulator instead of the other way around (and only at some extreme temperature). If bipolar transistors go into saturation (e.g. a current mirror not having enough headroom when the supply rail has not yet come up fully), this can inject carriers into the substrate and trigger latchup deep within a design nowhere near the pins.

I found that cutting traces with a laser on the probe station often caused latchup, so I used to defocus the laser beam and then go around the chip trying to latch it up with the laser, so that I could find the most vulnerable parts and then on the next revision I could improve things.

Well, that and cost -- just spam a couple commodity dice into the package and call it a day, versus making a precision (and quirky) monolithic that's never going to sell enough parts to justify its creation. (It's fortunate that a few monolithics do continue to exist, for the applications that /need/ those quirks -- but they are boutique items, and may drop at any time...)

Tim

You had a more refined approach :-)

Tim