Miniaturization

Exactly!

Tim

Shame on you... you're displaying your youth...

Before there was CMOS there was Bipolar (I'm talking early 1960's)... we had field oxide and metalization, occasional two-layer if you could afford it... and regularly did devices with 100um spacings between diffusions.

You're off on such a tangent you've forgotten the scale of things... if we drop back to such loose dimensions you might as well do a PCB with "chip-on-board". ...Jim Thompson

Great stuff. Find a bigger market for it and you're in business.

Until recently, LT1028 was a uniquely quiet opamp, well worth a few bucks to cut a product's noise floor by 3:1.

LTC3803 is a neat little switcher controller for about a dollar.

But I do use LT Spice to sim a lot of circuits that will not use LTC parts.

I'm not the one proposing to do it. I'd very much like a 100-MHz bandwidth laser noise canceller chip, and a fast sampler with an integrated sampling bridge and ADC would be interesting too.

Cheers

Phil Hobbs

I've been snarfing all the posted models I could get my hands on for awhile now--the mfrs have been sneakily encrypting models even for old devices. I have a giant library of all the parts I've actually used, so I just .include it in the .asc file while I'm hacking around, and then trim it down when I'm done.

Cheers

Phil Hobbs

The earliest ICs didn't have ion implants. They didn't have polysilicon. They didn't have oxide*. They barely had a metal layer. We don't need

*Gate oxide I mean. (Also, I forget if they used aluminum or degenerate-doped poly layers. Shame on me.)

Think big. Real big. Microns. Tens of microns, even. You can make a MOSFET as large as you want, as long as you don't mind its resistance being constant (same resistance/sq) and the transit time being proportionally higher.

Crappen up the material, too. (Is that a word? Doubt it. It could be.) Use poly-Si instead of single crystals! Performance is about two orders of magnitude worse, but so what? We don't need GHz for everything.

Yes, lots of cool things! Just imagine all the things people could come up with, if they had near-consumer-grade access to a worse, but still useful, process!

One can easily imagine how many piles of absolute garbage people will cook up, too, but there's no cost in that, not to anyone but themselves. There's no scarcity of resource. No need to think a "bad" design is somehow costing everyone else's time and money. Think 3D printing.

For God's sakes, people would make completely nonfunctional grids and patterns, just because they look cool! (Hey, printable diffraction gratings and holograms, why not?) What's wrong with that?

Tim ==========================================================

If you are going up to features in the 10's of um, would it be practical to go even bigger and put in some pads where you could wirebond down real transistors in bare dice form (or an op amp, or anything else available as bare dice), if you really had to have that performance in one part of your circuit but could live with homemade everywhere else? Make a hybrid instead of a chip. Just wondering out loud.

----- Regards, Carl Ijames

Are these things feasible on a chip? Why haven't they been produced?

Yeah, we all love to specify parts that are hard to use.

Some people are so paranoid that they are afraid to send us data sheets or give us pricing. Who are you? What is your application? How many will you buy?

I usually buy something else.

Sure. People make 90-GHz transceivers on a chip.

The laser noise canceller is sort of a niche market, though one I'm quite fond of. ;)

There are a lot of interesting subtleties to it: one design for a 10-MHz one that I've been working on uses active tweaking of the first three coefficients of the error polynomial (DC, j omega, and omega**2) in each of the three photodiode channels.

The mechanisms are quite interesting. For the j omega term, I use optocoupled MOSFETs to put resistance in series with each photodiode (which with the diode capacitance makes the j omega term). For the omega**2 term, I use gain peaking in an activated current mirror (a switcheroo Wilson, with a pHEMT amplifier holding the input node still so that its resistance doesn't change with photocurrent). Adjusting the compensation of the pHEMT loop with a varactor gives me a nearly pure omega**2 term out to the bandwidth I care about.

The DC tweaks are offset, of course, plus the log conformance error of the BJT diff pair, which is basically caused by R_bb'/beta + R_ee'.

The limitations of this are mainly due to the variation of electron transit time with position on the photodiode. The best ones I know vary by about 30 ps from centre to edge of a 1-mm PD, which is very good.

It's going to be very analogue-looking, except for having a button on the front marked "Optimize". You tweak up your optical system the way you want it, and hit the button, and your measurement magically gets up to 70 dB quieter out to 10 MHz.

That would be a lot easier to do with a custom chip.

Cheers

Phil Hobbs

I assume it would not be remotely affordable?

Dunno. I'm doing it on my own stick, so the NRE budget is, *ahem*, limited. ;)

Cheers

Phil Hobbs

Yes, that's why I said "depending on how ordinary the process was". I bet there will be someone who can make quarter micron pure CMOS in 30 years, but some exotic high voltage complementary bipolar process with fancy low TC resistors might get discontinued. Hence the appeal of banking wafers in that case.

I can assure you that there are 25 dollar chips of about the same area, made on the same process, in the same fab. One goes into a cellphone, one goes into some industrial equipment.

Not for the chips that I worked on, but it could be, e.g. if you insist on ceramic packages. Testing can be expensive too.

Still, if test and packaging are major costs and you want to do a lifetime buy, it is an argument for banking processed wafers rather than packaged, tested chips purchased from a chip supplier. You defer the cost of test and packaging until the products are required (if ever).

I have done discrete transistor circuitry and ASIC design, and I found that as a rule of thumb, I could get a given circuit topology to work with about 50 times greater bandwidth on chip (0.35um bicmos) than dead-bugged on copper clad FR4. This is not all about the transistor ft, mostly it is lower parasitics.

Lower leakage currents and nearly ideal oxide capacitors are nice too!

Also if you can show me where to buy a matched pair of transistors with a 48:1 (or similar) ratio of emitter areas, I will be very grateful. Having a large ratio of emitter areas is helpful in designing low noise bandgap references. Until recently it has been hard to buy a bandgap reference with < 10nV/rt-Hz noise (unless you buy it buried deep within a cellphone ASIC).

Chris

More like, find a market *and* investors.

"Jim Thompson" wrote in message news: snipped-for-privacy@4ax.com...

Me? Or did you mean Jon's quoted text?

That sounds like what I was thinking about. Early processes were "bulky" (~microns), diffusions with oxide and metal on top.

Did you mean 100nm diffusion spacings? (Also, is that depthwise, e.g. base width? That's easier to control than position on a ~um system, after all.)

What scale of things?

I'll gladly do CoB, that sounds great! Can you quote me an original chip design plus CoB packaging for $300 in qty 10? I have the cash on hand waiting!

Tim

Probably. Cheap hybrids would be an awesome midpoint. Do you know of any shops that'll prototype a module for $100 in qty 10?

(I said $300 in the other post, but hybrids aren't as small as in that example.)

If I can get 7 mil PCBs for $10, I should be able to get 3.5 mil PCBs for $20, or 2 mil for $40, or...

Please, prove to me why such is impossible. ;-)

Tim

The LT1028 has a curious noise hump at a few hundred kHz. It's in the datasheet now, but ISTR that it wasn't in the datasheet when the '1028 first came out.

The noise hump is bad enough to mess up your low phase noise PLL or laser diode noise canceller or whatever.

Regards, Allan