Mineral Oil as Thermal Grease

Somehow lost the entry for Liquid Metal. Here it is:

Liquid Metal k = 73 T2 = 25.021

The shear stress goes as 1/thickness.

Cheers

Phil Hobbs

I should qualify this. For a very thick bond line, the local stress at the surface depends on the CTE mismatch between the adhesive and the adjacent surface, and not on the CTE of the other surface.

As the bond line gets thinner, the effect of the other surface is felt more and more, constraining the softer adhesive's ability to redistribute stress, and turning shear stress at the edge into a very large tensile stress.

For instance, if you have a 100-nm bond line, and the CTE mismatch produces 1 um of shear at the edge, the adhesive would have to elongate

With a 25-um bond line, the local elongation would be only about sqrt(1+1/25**2)-1 ~0.8%. (You'd have to worry about Poisson's ratio and the equilibrium shape to figure it out exactly.)

Cheers

Phil Hobbs

Yikes, 100 nm is optics. We're just heat sinking mosfets.

I wonder how flat a typical mosfet tab is. I just tried a TO-247; the epoxy around the metal tab is above the tab, which itself forces a gap to the heat sink. The difference seems to be a couple of mils.

On a couple of other fets, the metal is above the epoxy. But none looked like optical finishes.

Not exactly; MOSFETs come packaged with a metal slug, some CPU and other LSI chips come with a silicon surface exposed. There's differential thermal expansion (and temperature gradients) in these materials, so it all flexes and stretches slightly. You need a soft interface layer to take up the stress, or that strain shows up in the die.

MOSFETs will have metal slug/bear-grease/die sandwich preassembled, so there's some compliance in the bear-grease part. You might get away with no other protection for the die. On a CPU/thermal-compound/heatsink, the thermal compound is a more important element of the mechanical problem than it is on a MOSFET.

Nah, an optical finish is a lot smoother than that, at least on small scales. Ordinary float glass is ~500 nm per inch flatness, with surface finish of a nanometre or two, iirc.

The point is that for bond lines, too thin is even more of a problem than too thick.

A micron isn't a lot of expansion. A 1-inch square of metal with a CTE of 40 ppm expands that much _per degree_. A 1-um bond line will get into trouble pretty fast unless the surfaces are reasonably CTE-matched, or the glue is comparable to them in Young's modulus.

Cheers

Phil Hobbs

Actually not--if you don't constrain the differential expansion of the chip and the substrate, you'll delaminate the solder balls in the corners of a big chip. That's why they use hard epoxy underfill.

Nope. For chips with high dissipation, the die attach is done by eutectic brazing or else silver epoxy (only for high-value parts). So I'd expect power FETs to be brazed.

CPUs generally use paste thermal interfaces.

Cheers

Phil Hobbs