I like to make small SPICE models of parts, derived from analytical expressions of a few critical things that're going on in the aspect of the circuit I'm evaluating.
For example, consider an op-amp driving a power MOSFET to create a controlled current source. The FET's high gate capacitance, along with the bootstrapped source resistor, creates a confusing control loop. My RIS-796, a 250-amp LED pulser project, uses this. If you want, sets of files:
In AoE x-Chapter 4x.26, we struggled and derived a set of analytical equations for this circuit. See article here.
The circuit basis for the equations uses the MOSFET's gm, equation id = gm (vg-vs), and its gate capacitance, Ciss. The equations are hairy. But we also suggest you can make a simple SPICE circuit with the op-amp, the FET's id and Ciss, plus additional Rs and Cs, to evaluate the circuit.
Such a scheme may only works well over a limited range of conditions, e.g., using the value for gm at the FET's 250A current, means that the reduced-current startup won't be accurately modeled. But it's still quick and useful. And you can repeat the SPICE run, with lower values of gm, to get an idea of what's happening during the pulse startup.