Meaning of "dynamic clock"?

More properly, it has dynamic logic. DL depends on charge being held on internal nodes from sheer capacitance. If you clock it too slow, bits leak away and it messes up. This was used to save power in older, all pmos or all mnos, chips, where resistive or depletion loads wasted a lot of power. CMOS is usually static.

This becomes a "flipflop" if the clock is pulsed

logic in------- ---------------out | | ------- --- | | | clock

where just stray capacitance holds up the output when the fet is off. Chips like this often used multiphase pulsed clocks to pull off tricks like this.

John

It could mean several things, but in this case I'd take it to mean the device used dynamic (or Domino) logic. Basically, once a cycle the state of a node is forced to say '1'. Later in the "cycle" if an event occured the node was pulled to a '0'. If the event didn't occur, the '1' remained. Now string these together (alternating '1's and '0's as the "precharge" state). It is dynamic because the vaue is stored on the node's capacitance.

See above. The value of the internal nodes is stored on a capacitor, which leaks. P/NMOS designs used dynamic logic pretty much exclusively. CMOS can be made "static" (all state held on full latches, domino logic is still present in many CMOS designs for space/speed reasons. These designs will also have a minimum clock rate.

Yes, though it's dynamic logic internal to the device.

No, not the clock and not capacitively coupled or differentiators of any kind. The data is stored on (parasitic) capacitors rather than using full latches.

ance.

Dynamic logic saves components too in CMOS. You don't need all those P devices to mirror the N devices. I'm not sure I'd consider it old, if by that you mean, it isn't used anymore.

VLSI CMOS is usually *not* static. Very few high end microprocessors are fully static and usually do contain at least some domino logic. It's faster, smaller, and uses less power than a fully static design.

I suppose that's true for things like Pentiums and graphics processors. The embedded CPUs and FPGAs that we use are fully static, with the exception of some PLLs and such.

So "usually" becomes a statistic.

John

Right, because the benefits of domino logic dont' matter to N-10 technology. FPGAs pretty much have to be static. The tools are a nightmare even with static logic..

Products that are not on the bleeding edge tend not to use bleeding edge design techniques, no.