max. current through a 4066 switch

Without package strays... silicon only. 50 ohm load helps as well ;-)

...Jim Thompson

Reviewing that, looks like the simulator couldn't cope with Fourier of the TRANSIENT output because it doesn't match with what you would expect from a .AC analysis.

(This was back in 1999-2000... probably PSpice Release 8.)

...Jim Thompson

Dual-gate mosfets work well too. In the palmy days, I used to use a lot of 3N201s for sampling.

Cheers,

Phil Hobbs

Ron spread, anything else they dont mention in the datasheet that you think is interesting/useful.

Cheers Terry

I need to translate current to voltage at a virtual ground point using an op-amp with switchable feedback resistors spanning 7 decades. The feedback resistance for the highest current range (+-100mA) is 20 ohms, and for the lowest range (+-100nA) it is 20Mohms.

I know the easy way out is to use a reed relay for each resistor, but in hope to reduce board space I'm wondering if a fully analog switch approach would work. The off state leakage of 4053 series is specified at

My current thinking is to go for a reed relay only for the 10mA and

|\\ GND---|+ \\___________ Iin--o--|- / | | |/ | | | | / | o--20M--o--o' o---o | | | | '------------> mux2 ch6 | | | / | o--2M---o--o' o---o | | | | '------------> mux2 ch5 | | | / | o-200k--o--o' o---o | | | | '------------> mux2 ch4 | | | / | o--20k--o--o' o---o | | | | '------------> mux2 ch3 | | | / | o--2k---o--o' o---o | | | | '------------> mux2 ch2 | | | / | o--200--o--o' o---o | | | | '------------> mux2 ch1 | | | / | '--20---o--o' o---o | '------------> mux2 ch0

"Jim Thompson" a écrit dans le message de news: snipped-for-privacy@4ax.com...

ROFL... page 12, 100kHz, 50R load isolation test: -350dB (Ziso = 1.6 10^19 or Cpar =

I want you to design me a 10GHz switch with 200dB iso. That should leave you a nice 50dB margin :-)

Hi Jim,

thanks for that. very interesting, esp. that strays dominate crosstalk. that always seems to be the case.

Cheers Terry

Trying to decipher (after 5 years) what went bad, looks like it was the Probe Macro "VdB" that was defective.

This was all done in a month, scrambling like mad. Customer (Motorola/ON) didn't say "boo" at the design review ;-)

Particularly jumps out at you when you look at the capacitance simulations :-(

The products ARE in production SUCCESSFULLY ;-)

...Jim Thompson

Just the gravitational attraction between electrons would give more feedthrough than -350 dB. I guess Spice doesn't model that.

John

'LVX' versions....

...Jim Thompson

...

Well, everything, of course! :-)

Thanks! Rich

"Jim Thompson" a écrit dans le message de news: snipped-for-privacy@4ax.com...

Cpar =

you

Then I'm still amazed. I we allow 10fF of silicon strays the figures should be -130dB. Plus the pb with FFT isn't the absolute level but when the harmonics relative level is too low wrt fundamental. Here we have a full flat: probably a missing input signal. But what really cought my attention is: is that this report that you gave your customer? He should have pointed this out within a picosecond, more or less :-) What is a realistic Cds stray?

Now I'm curious: for gates like this do you run a post layout sim with extracted parasitics? Do you do it all the time or which criterias do you use to decide to do it or not?