Low voltage shunt regulator

Yep...

...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    | 
| San Tan Valley, AZ 85142     Skype: skypeanalog  |             | 
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  | 
| E-mail Icon at http://www.analog-innovations.com |    1962     | 
              
I love to cook with wine.     Sometimes I even put it in the food.
Reply to
Jim Thompson
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I program the output voltage

You're confused. Your feedback is a voltage to current conversion so this v olt-for-volt feedback you think you have is a fantasy. Also, the feedback a ttenuation is the same unless your dealing with large currents. It is more power conservative to use a high voltage reference than a high current refe rence.

Reply to
bloggs.fredbloggs.fred

Got a schematic that works that you can show us ?? ...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    | 
| San Tan Valley, AZ 85142     Skype: skypeanalog  |             | 
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  | 
| E-mail Icon at http://www.analog-innovations.com |    1962     | 
              
I love to cook with wine.     Sometimes I even put it in the food.
Reply to
Jim Thompson

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FET or whatever for some micro second. When stable sample the voltage onto a capacitor and turn the pulse off. Wait a looooong time and do it again. T he average current is whatever the sample circuit dictates

Something like this:

formatting link

I was in a rush, so didn't tweek the values or set the corrent dutycycle, b ut the idea is shown

Regards

Klaus

Reply to
Klaus Kragelund

[snip]

I thought you were going to show me how to do all that as a two terminal shunt regulator ;-) ...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    | 
| San Tan Valley, AZ 85142     Skype: skypeanalog  |             | 
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  | 
| E-mail Icon at http://www.analog-innovations.com |    1962     | 
              
I love to cook with wine.     Sometimes I even put it in the food.
Reply to
Jim Thompson

Well, you are the IC designer, right? So just make a new IC for the world :-)

Reply to
Klaus Kragelund

As an I/C design, it would be trivial with today's processes.

Nobody has done a really good CMOS remake of the TL431 or the LM185. It would be easy enough to do it on just 1uA of quiescent current.

(In the past few months I posted comments about some of my recent designs: a 1kHz oscillator running on 6nA and a 1MHz oscillator running on 1.3uA) ...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    | 
| San Tan Valley, AZ 85142     Skype: skypeanalog  |             | 
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  | 
| E-mail Icon at http://www.analog-innovations.com |    1962     | 
              
I love to cook with wine.     Sometimes I even put it in the food.
Reply to
Jim Thompson

:)

Reply to
Maynard A. Philbrook Jr.

I have used that scheme in the past. It certainly can be made stable, but I think that there are other schemes that can respond to and correct disturbances faster. (e.g. in your current sink, if the drain voltage changes and the MOS goes into or out of triode, the source current will change and the feedback loop could take a while to react.)

I am presently investigating whether an available OTA chip is a good solution, and whether its dynamic performance can beat that of the circuit you suggested. Certainly if you are not designing chips, an op-amp is easier to get, with more choice of parts. I doubt an op-amp would be the best option if the circuit were being put on a chip allowing you to have gm stages as easily (or more so) than complete op-amps.

Chris

Reply to
Chris Jones

I may have expressed myself in a confusing manner, but the circuit behaves as I expect it to in LTSpice so I had better try explaining it again. (When I have removed a bunch of irrelevant cruft like test harnesses for stability checking, then I could post the .asc which would allow you to simulate how it works also.)

My point about the volt-for-volt feedback is that if you take the drain, at 400 Volts, and feed it into a 99M:1M resistive divider, you will get a 4-volt signal that you can use as feedback into one side of the differental voltage input of the gm-stage (voltage to current converter) that drives the gate capacitance of the MOSFET. This will work, but for each volt of error at the drain terminal, you only get 10mV of error at the input of the gm stage, which with the OPA861 having a gm of about

100mA/V will give you 1mA of gate current to charge the gate capacitance and miller compensation capacitor on the MOSFET.

If, instead, you take your feedback from the drain of the MOSFET with just the 99M resistor, and instead of connecting that to a 1M resistor to ground, put a 4uA current sink instead, then when there is a 1 Volt error in the drain voltage of the output MOSFET, there will be a 1 Volt error in the 4V signal at the other end of the 99M resistor. You can put a capacitor across the 99M resistor so that it doesn't add another pole. Of course you need a very low input current voltage buffer between the

99M resistor and the B input of an OPA861, because it has quite high input current otherwise. That buffer needs to be fast enough not to have significant phase shift up to the frequency where the loop gain has rolled off to less than unity, and it seems quite feasible to achieve that.

I hope that is a clearer explanation. If not, maybe I will get around to uploading a .asc file some time.

Chris

Reply to
Chris Jones

MOSFET or whatever for some micro second. When stable sample the voltage on to a capacitor and turn the pulse off. Wait a looooong time and do it again . The average current is whatever the sample circuit dictates

, but the idea is shown

Oh, if you meant the TL431, then replace the zener with the TL431 (I had li tte time to draw all the details)

Cheers

Klaus

Reply to
Klaus Kragelund

In this case, he answer is "no"; it will be kept outside the oven and at a relatively constant temperature, nominally designated as "room temperate".

Reply to
Robert Baer

Actually, that is more readable since the contrast is mucho besser, and militarily uniform (no starch).

Reply to
Robert Baer

Huh? 100uA is a lot more than 20uA, and pulsing is not quite the same as DC.

Reply to
Robert Baer

Here is another case of a quite readable drawing with good contrast, and uniform background.

Reply to
Robert Baer

On a sunny day (Fri, 22 Aug 2014 18:27:03 -0700) it happened Robert Baer wrote in :

You finally bought a 21 century monitor?

Reply to
Jan Panteltje

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SFET or whatever for some micro second. When stable sample the voltage onto a capacitor and turn the pulse off. Wait a looooong time and do it again. The average current is whatever the sample circuit dictates

.

Well, the current is 100uA for only 10us. During that time the voltage on t he reference is sampled by a storage capacitor which holds the reference vo ltage between samples. The source is then turned off and the current is 0. (except for the 4-5uA for the opamp.

So the average current is less than 10uA, depending on how you make the S/H and how long hold time/period you define

Updated schematics, repetitive S/H:

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Cheers

Klaus

Reply to
Klaus Kragelund

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MOSFET or whatever for some micro second. When stable sample the voltage on to a capacitor and turn the pulse off. Wait a looooong time and do it again . The average current is whatever the sample circuit dictates

DC.

the reference is sampled by a storage capacitor which holds the reference voltage between samples. The source is then turned off and the current is 0 . (except for the 4-5uA for the opamp.

/H and how long hold time/period you define

The gate charge energy for the level shift for the FET add to the average c urrent consumption, so one would need to reduce the current of the S/H as m uch as possible and/or optimize the droop of the sampled voltage, so that t he entire cycle period is long.

Cheers

Klaus

Reply to
Klaus Kragelund

Sample-and-holding is only a valid approach if the load current stays constant between samples. ...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    | 
| San Tan Valley, AZ 85142     Skype: skypeanalog  |             | 
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  | 
| E-mail Icon at http://www.analog-innovations.com |    1962     | 
              
I love to cook with wine.     Sometimes I even put it in the food.
Reply to
Jim Thompson

wouldn't all that make the overall response of the shunt regular slow?

Jamie

Reply to
Maynard A. Philbrook Jr.

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