Low bias current opamps

Cool. I had not noticed that they had gotten that good either, but it did not surprise me. How is the offset voltage?

?-)

C.

Plastic: 1e16 ohms. Ceramic: 1e14 ohms. Pease says so.

James Arthur

They pound the crap out of the mil spec devices during testing, probably. Back in the JANTX days that was a real problem with some transistors--the COTS versions were more reliable because they suffered less abuse.

Cheers

Phil Hobbs

I found a spec for ceramic, which runs 1e14 to 1e16 ohm meter. Did Pease drop the units?

In a ceramic package, you generally solder the die bottom to the metal inside the package. [I think they call it a scrub. I've never that step done.] Now since the resistance is volumetric, the metal on the inside of the package certainly has a decent contact to the ceramic. Actually it approaches the ideal metal plate used in the typical description of how you define volumetric resistivity.

In a plastic package, the part sits on a paddle in the leadframe, which can be isolated. But it also has contact to the plastic. Visualizing this, it seems like both packages have significant contact to the insulating material.

But it is possible in a plastic package to put the chip on "glass beads." That floats the substrate contact. I don't know if that scheme is possible for ceramic packages. Obviously if we had a packaging engineer on the list it would be far better than someone who has just had chips packaged.

I haven't found a spec on the plastic resistivity.

Am 10.11.2012 01:36, schrieb miso:

The sealing glass in those cheap non-sidebrazed ceramic Eproms produced so much water during fritting that it already was corrosive.

regards, Gerhard

Actual testing for commercial parts is limited to basic function, often on wafer. Industrial parts get tested at 25 C and maybe at high temp, usually after packaging, no real process difference except test failures are usually dropped back into commercial bins. Military grades require much more bookkeeping. Generally only "selected wafers" get a chance to be Military grade.

The goop would have to be much less expensive that package plastic or preserve exotic properties like ultra low leakage.

?-)

The goop is something to do with packaging in general, not low leakage. Not everyone uses it.

Wafer test is simply to save packaging parts that will fail at final test anyway. Nobody, or at least no place I ever worked, packages parts and didn't test them. Plenty can go wrong in backlap, bonding, packaging, etc.

Everything with electrical limits is tested at ATE at all grades at room temp for packaged parts. If you look carefully, you may see GBD (guaranteed by design). That can mean a lot of things. If it is a capacitance at a pin, the assumption is if the wafer passed parametric testing, then the pin capacitance will be totally predictable, hence GBD. If the part has a reference in it. the drift at elevated temperature in theory can correlate to the drift at cold temperature.

All the tests have guardbands. Depending on the company, some test wide at wafer then accept the rejects at final. You do this is the chips are expensive. That is, you are willing to spend some money packaging borderline parts in order to get product to sell. The other scheme is to test tight at wafer and then have looser limts as the part goes down the test flow. That is, the test limits are tighter than the datasheet spec at wafer. At QA, the test limits are exactly what is on the datasheet less the bench to ATE correlation error. That is, somebody should be able to bench test the part and have it pass publsihed electricals.

If you are not familiar with parameter wafer testing, the devices on the test pattern have to meet test criteria before product wafer testing is done. If something fails the parametric test, then a decision is made to see if the parts are OK to sell in terms of reliability. That is, say the oxide breakdown was out of spec. You would probably reject the wafer just because you don't trust it. Put if a parameter is off on a device you don't use (say epifet), then the wafer can go off to production wafer test.

Interesting, thanks.

IIRC the goop is generally RTV silicone, which greatly reduces die stress due to epoxy shrinkage and temperature cycling. That's often recommended for people who want to pot their circuits in epoxy--a layer of RTV underneath prevents stuff getting torn off or cracking when the epoxy cures. OTOH for chips, the RTV will make the package floppier, which might increase die stress from external effects.

Cheers

Phil Hobbs

Lots of chip packages are so thin there can't be room for a filler inside.

Fun: push here and there on an opamp or a DAC with a pencil point and watch the DC offset change.

I thought the original reference was to polyimide (Kapton, Parylene) film, baked onto the surface to exclude reactive ions (like, from moisture). It's a VERY thin film.

There are layout tricks to get around the pressure effect, but they take up space. One scheme is named after an annoying pop music group: ABBA. I have seen texts where the layout is done in a manner to match the orientation of the wafer. I've never seen that done in real life.

Surface mount parts get a lot of backlap. If you don't know about backlap, here is my attempt at an explanation. I don't know the "deal" exactly, but the fab picks a wafer thickness they believe will stand up to the rigors of processing, probably handling issues. Often that is too thick for the package, so they grid the wafer down to the right thickness after it has been wafer tested. This is an outside service, at least in my experience. [TI could be an exception since they are known for doing much work in house.] I have seen a lot of product over the years screwed up by using the wrong backlap spec. Outside vendors are always a problem. One place I worked was too cheap to own their own ion implanter and often the outside service would miss an implant or do it twice.

The thinner the dice, the more likely the pressure effect will move the offset.

Prior to everyone using epi wafers, some fabs would ion implant the back of the wafer to reduce resistivity. That sounded like a plan, but ion implant isn't all that deep, so backklap would alter the bulk resistivity in the final product.

The "goop", more commonly referred to by us in the industry as "greased pig snot", is mostly for (1) stress relief of wirebonds, (2) to keep wirebonds from "touching down", and (3) to keep the wirebonds from being pushed/stressed during the injection molding. ...Jim Thompson

Back in the day, components (mostly diodes) were labeled as "glass passivated". I believe I have also heard kapton being a prevalent method these days.

Tim

Parylene is usually evaporated, so it would be hard to keep that off the leads.

Cheers

Phil Hobbs

going

film,

Dunno, just goop does not sound like a thin film to me. OTOH i would like a better reference than some goop on some parts.

?-)

method

Hmmm. "Glassivation" (tm) is from the early 1960s or before. I don't think Kapton became popular until the 1980s.

YMMV

?-)