Looking for two-input comparator with hysteresis

You are trapped into thinking about steady state. It is the transition between steady states that causes the error to accumulate over the long term. The '339 circuit pulls nonlinearly with line amplitude. Therefore it will accumulate error.

Eh ? Come again.

Graham

it.

OnSemi specs... +-20 mA. Fairchild is reasonably close, +-20 mA. Now Philips, on the other hand, specs their abs max esd diode current at

+-20 mA, but the real goofballs are those whacky Italians at ST who for some reason spec theirs at +-20 mA.

I *wish* these people would get organized.

John

Sure, feelings are what really matter.

John

Having once experienced device latchup thanks to a certain person's secret 'contribution' to a pcb layout, I prefer to 'play safe'.

Graham

OK, if 5,184,000 sine cycles go into the comparator every day, and

5,184,000 square cycles come out every day, where does the error accumulate?

John

It's sure got me beat !

Graham

Some parts do still latch, especially mixed-signal stuff. The LM35/LM45 temperature sensor are horrors, and a lot of ADI and BurrBrown ADCs and DACs are ghastly as regards latching on overdrive or improper power-supply sequencing. I've seen systems where a uP could power-cycle a DAC if it suspected it had latched.

74HC parts are pretty well hardened these days. A few will latch at extreme esd diode currents, enough to be dangerous in their own right, and some won't latch at all.

We just did a product where it was really convenient to current-limit a customer input with Supertex depletion-mode fets (to around 1 mA max) and dump that into an ADI chopamp, letting the esd diodes clamp on overvoltage. We tested the parts pretty hard to make sure they didn't mind, and powered them from shunt regulators to limit supply current.

Esd diodes are free, so we've just gotta use them!

John

Uhuh. In my case it was an MDAC. And the issue was a brief voltage spike betwen logic and analogue 0V at power-up. caused by a supply decoupling cap ( that wasn't on my schematic and got added by the 'helpful guy' ) charging in fact. The associated trace and current created enough volts across it's resistance on power-on to latch the chip. Luckily they didn't break but just got very warm.

I take your point.

How long did the testing take ( cost ) vs using other methods to clamp the volts ?

Makes me cringe though.

Graham

On Wed, 24 May 2006 22:12:24 +0000, Christopher Tidy wrote in Msg.

Don't think potential here. You might even omit the capacitor. Your circuit is relying on the input protection diodes of the schmitt (check your data sheet) to limit the input voltage. The cap is just there to filter out multiple triggering by runt pulses on the AC line.

robert

On Fri, 26 May 2006 00:26:55 +0100, Pooh Bear wrote in Msg.

Not necessary, as I already pointed out. Let the voltage be clamped by the IP diodes. The resistor is just a current limiter, with some filtering action thrown in by the cap.

robert

On Wed, 24 May 2006 23:12:50 -0400, krw wrote in Msg.

I just can't see the point of using an optical insulator fore *safety* reasons in a circuit which has both sides of the insulator connected galvanically anyway. If the transformer insulation fails, the whole circuit is live. On both sides of the isolator.

robert

When the mains amplitude climbs to a new magnitude, the '339 triggers increasingly early during the cycles comprising the transition- and "early" is relative to the trigger period prior to the amplitude change. These trigger period transitions will be different from those due to a mains amplitude decrease, because of the waveform input to the '339. Mean trigger cycle perturbations do not zero- they accumulate- the circuit is weighting the perturbations due to mains amplitude decrease by more than the increase. And even if the weighting is equalized, there is no reason for the mains fluctuation to zero, it will be a function of the energy profile of the grid.

Who are you and what have you done with 'Fred Bloggs'?

Best regards, Spehro Pefhany

--
"it\'s the network..."                          "The Journey is the reward"
speff@interlog.com             Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog  Info for designers:  http://www.speff.com

volts ?

Just an hour or two. Explicit clamping would take room (the circuit is very tight), add more supplies, complicate headroom and linearity issues, and add leakage in a circuit where we begrudge every picoamp.

A Real Man does what he Has To Do.

John

Thanks, Speff. You saved me a lot of typing.

John

What BS!

...Jim Thompson

-- | James E.Thompson, P.E. | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona Voice:(480)460-2350 | | | E-mail Address at Website Fax:(480)460-2142 | Brass Rat | |

| 1962 | I love to cook with wine. Sometimes I even put it in the food.

Nah, if you look closer they're all digital (see: Plank). ;-)

--
  Keith

It's fairly common, actually. The mains frequency is far better than you're likely to find at a reasonable cost otherwise.

--
  Keith