I have to generate a series of 5MHz pulses from present 50MHz pulses, i.e., take one pulse from every ten pulses. Apparently the counter chips I have now are not fast enough for 50MHz. Can anyone recommend a faster one or any way that could handle at least 50MHz? Thanks.
Anne
What counter devices do you have now? The toggle rates of the newest versions of FAST / FACT are well up to the task. If you want to go the whole hog, you could always use ECL (but it should not be necessary).
I suggest looking closely at the Fairchild / TI sites.
Cheers
PeteS
ECLinPS can do 500MHz, but it would be a bit of an overkill for the job.
A chunk of fast programmable logic is probably the easiest way to handle the task.
Peter Alfke - a Xilinix applications engineer - hangs out on comp.arch.fpga and was talking about 200MHz fully synchronous counters a few years.
Farnell stock some 7.5nsec Lattice parts which might be good enough for
50MHz - I've not played with them at all so I've got no idea how they'd stuck up in reality, but someone on comp.arch.fpga will probably be much better informed.-------------- Bill Sloman, Nijmegen
50 MHz is nothing for newer programmable logic. Xilinx makes a bunch of PLD's that can handle a simple clock divide down at this speed. I notice that no jitter specification is given by the OP, so I assume it is non-critical.
--Mac
Which is it? View in a fixed-width font such as Courier.
. . . . 1 2 3 3 5 6 7 8 9 10 1 . -- -- -- -- -- -- -- -- -- -- -- . | | | | | | | | | | | | | | | | | | | | | | . | | | | | | | | | | | | | | | | | | | | | | . -- -- -- -- -- -- -- -- -- -- -- . . . . EVERY 10TH PULSE LOOKS LIKE THIS: . . -- -- . | | | | . | | | | . -- -------------------------------------------------------- - . . . . . . 5MHZ LOOKS LIKE THIS: . . . ----------------------------- -- . | | | . | | | . -- ------------------------------ . .
This is bad advice. The 83MHz is the "typical" maximum frequency. The guaranteed worst case maximum frequency is 25MHz, and that is what you use when you are designing anything.
In fact, even the 74ACT163 won't quite make 50MHz - the sum of the worst case clock to carry out propagation delay plus the parallel to clock set-up time is 21.8nsec where you'd need 20nsec of less to get every tenth pulse out of a 50MHz pulse stream.
---------------- Bill Sloman, Nijmegen
Matt Roberds
The Altera CPLDs, eg MAX3064 have 64 flipflops that can be used for synchroneous counters up to 120..200MHz, depending on the number of bits used. Competitors have similar chips. Getting used to this stuff requires a few days to spare though.
Rene
Right. The 74VHC163 will almost do the job on its own. You get a roughly 10nsec wide positive going pulse out of the terminal carry (TC) output - if it was negative-going you could use it to drive the parallel load input directly, since the worst case propagation delay and minimum set-up times only add up it 17.5nsec, but putting in an inverter to get the polarity right would add enough propagation delay (5,5nsec) to eat up all of your 2.5nsec safety margin.
As you say, adding in a 74HC74 to pipe-line and invert the TC output lsolves the problem and leaves you a bit more safety margin - the worst propagation delay from the 74's clock to output at 5V is only 10.5nsec,
1nsec faster tham the worst case 5V clock to TC propagation delay for the 74VC163.----------------------------- Bill Sloman, Nijmegen
Duh- the 74VHC family does 185MHz, available in SOT or DIP from Mouser, Fairchild Semi in stock unit quantities available for immediate shipment, runs about 75 cents per part. Anne, doesn't express herself very well, so no suggested circuit will not be forthcoming- the 74VHC163 in combination with the 74VHC74 will do well for a 50/50 5MHz with lots of room to spare for worst case Tpd's and Tsu's, 15pF loading, and Vcc=5V- the other interpretation of her requirement not so easy.
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