The cap does make some difference in the rise time, especially if the clock signal has an added source termination resistor. Your are right that it is not a big change, but it doesn't take much when dealing with these high-strung FPGA inputs.
If there was enough ringing on the signal to cause double clocking, indicating that the clock signal was poorly terminated, then John would have seen this on the DSO. The FET probe capacitance would not have made this invisible.
In John's case my money is on crosstalk.
In the OP's case, it could be any one of several things.
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Greg Neff VP Engineering
*Microsym* Computers Inc. snipped-for-privacy@guesswhichwordgoeshere.com