LC circuit

"Jessica Shaw"

** That is just not readable.

Forget Imageshack - it's a PITA.

... Phil

No, it won't. The voltage at the sources will only go about a volt above the 12V supply due to the body diodes.

The HIP 4081A is rated to only 80V.

Did you read any of the replies in your OP of subject: MOSFETS and H bridge ??

Hi,

I see 400V peak to peak when I put oscilloscope probe across the load, not from source to HIP chip ground. When I probe the Source terminals of the upper side NMOSFETS than I see 12 volts. What I am thinking is to Turn ON the pair of transistor and turn them OFF before the voltage reaches its +ve peak voltage value than turn ON the other pair and turn them OFF when the LC circuit its maximum -ve peak voltage value. I tried to use the independent timing mode and disable timing mode but the lower side MOSFETS turns OFF quickly than the upper high side MOSFETS. The gate voltages of the lower side MOSFETS falls sharply than the gate voltages of the upper side MOSFETS.

The gate voltage takes about 4usecs to go to zero. First, it goes to

22 volts than drops to 12 volts and than stays at 12 v and than goes to zero. I am trying to put the complete schematic that i used soon. I did post the schematic but its not readable.

I disconnected the AHS and BHS pins from the sources of the upper side MOSFETS and tien them to +12v just to let the chip know that 12 volts are there but the chip loads my power supply and bring it to 8 volts.

jess

Then why does your original post say:

"I am expecting to get the 400 Volts peak to peak voltage across the load. This voltage will appear at the source terminals of the NMOSFETS ( upper High Side)."

?

Hi,

My bad. I uploaded the better image of the circuit diagram. The link is given below

Circuit Diagram

waveforms link

jess

I forgot to mention that the pins AHI and BHI are connected to +12 V for independent timing mode. But they are not connected to +12 V in Disable and bistable modes. jess

I don't know that chip well how ever, have you increased the size of the charge pump caps for the high side? Have you lowered what looks like R's coming back from the SOURCES?

Also, if you can, you should be generating a null session before allowing the other side of the bridge to active, in other words, don't allow for shoot through and add a snubber across that when you do.

Btw, have you selected the proper diodes to be used when discharging the gate from the driver? You do need diodes with fast switching, UF diodes come to mind.

Jamie

Okay. It makes a bit more sense. What devices are you using for M1-M4? What is Cgs?

First, show the schematic of your "load" or describe it in detail. That is, what is R, what is L, what is C. If you don't know, please indicate as much and give whatever info you have available.

If I make certain (probably invalid) assumptions, your load consumes about 3.6 watts (300mA at 12V, you said). You have a series LCR between the bridge load points (if not, tell us). The supply voltage is 12V so that the load sees 24V peak (square wave). You are running at 100kHz and the reactive components are resonant. The fundamental AC applied to your load will be about 10.8V. Since you say you see about 200V peak across one of the load components, it means that your circuit Q is about 13 because of the voltage boost.

Based on the above, I would guess that you have a series connected load of about 675uH, 3.75nF, and 32 ohms.

If none of this is in the ballpark, lets start over.

Next, your waveform info is confusing. When you indicate low side and high side, you must distinguish between left and right sides. If your waveforms are correct and you are showing the gate drives of two FETs on the same side, you are shorting your supply every time you turn on the FETs.

John S

Hi,

I am using IRFB4115GPbF NMOSFETS. The Qgs is 28nC. The waveforms that I posted are correct. I might labelled them little wrong. Its the high side A with low on B side. Its a pair. My load is just LC circuit. I do not know the value but L and C are resonant with each other.

jess

Hi,

I even removed the diode and it shows me the same waveform that i posted on gate voltages of the transistors.

jess

Concerning your waveforms,

What is the width (in microseconds) of the upper side gate voltage when it is 22V?

What is the width (in microseconds) of the upper side gate voltage when it is 12V?

Are you, by any chance, driving the ALI/BLI inputs with a duty cycle of less than 50%?

Hi,

approximately 1us when +22V and approx. 4usec when its 12 volts. 40 percent duty cycle.

jess

Aha! That's why the gate drive waveform looks as it does.

It should NOT appear as you suggest at the bottom of your waveform picture. To me, it looks normal. Do you know why?

Your schematic looks acceptable at this time.

Are you using duty cycle to limit the freewheeling 400Vp-p you mentioned? It appears that your circuit Q is much higher than I predicted mainly because I assumed you were running 50% duty cycle. For example, what is the fundamental voltage of a waveform having the characteristics you supplied?

Can you disclose your objectives rather than have us read data sheets and guess at everything?

Try doubling HDEL/LDEL and observe performance. A dead time of 100ns vs

50ns out of 5us will not affect you much and will give everything in your circuit time to settle down. Maybe even reduce shoot-through (when you decide to run 50% duty cycle, if that is the objective).

Are your FETs on a heatsink? Can you hold your fingers on them? Do you have a way of reading their temperatures?

What is the normal operating current from your power supply before things go bonkers?

How much power are you wanting to supply? From everything you have posted so far, you have indicated almost none. Is this just the first stage in trying to build some kind of power supply but you have not even put a load to it? The FETs you selected are capable of so much more, so it seem senseless that you only want to drive a nearly lossless resonant circuit which you could do with pretty low end FETs.

Please answer the above questions item by item and then consider the following:

Get rid of any slow diodes (1N400X are not the best at 100kHz). Get rid of the snubbers on the FETs. If you want snubbing, use Schottkys around the FETs (yeah, I know the FETs have integral diodes, but you MIGHT benefit a little from the lower Vf of Schottkys). Also, you are conceivably seeing up to .3W from the snubber dissipation. Use high speed silicon diodes for the charge pumps. Be sure your 12V supply is well filtered and can handle the temporary energy dump from your load (make your supply bypass C in the uF range with HF bypassing as well).

John S

How do you know? How have you determined that the load is resonant? Is it series or parallel resonant? It can make a huge difference.

You need to know your load characteristics in detail in order to understand your circuit operation. For example, if your load is parallel resonant, you will have large switching currents.

Also, note that no resonant circuit is without resistance. How much do you have?

Show on your schematic where you see the 400Vp-p, please.

Hi,

I used faster diodes (UF 4007) and using new transistors with Vds voltage 500 Volts and Id = 100 A, 2500 Watts Transistors. All timing waveforms and the gate waveforms looks good with out the load but with the attached load, gate waveforms look screwed up. The transistors are getting really hot but getting hot. The peak to peak voltage is almost

390 volts, power supply is 12 volts and showing about 1.6 A current draw.

The schematic of the load can be found at the following link

Any suggestions!

Thanks Jess