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Latching solenoid driver (H-Bridge)

Hi all,

I'm currently designing a circuit which has to drive a latching solenoid. This solenoid is part of a machine and will "lock" a pluggable external device. This circuit must remain low cost but robust too.

The circuit works as following: At the start of the machine, a test is done in order to define if the solenoid has been damaged (open-circuit behavior) and must be replaced. During this test, the solenoid is powered with a voltage < 6V to prevent it to activate and the current through it is measured with a sensing resistor.

After this integrity test, the user can plug the external device into the machine: the solenoid act as a lock under 24V (latching).

The user can unplug the device after its use or if an error occured: the solenoid is unlatched under 24V (reverse voltage).

SPECIFICATIONS Solenoid:

  • ESR = 14.11? * U < 6V (during integrity check) * U = 24V (latch/unlatch) * Pulse Ton >= 1ms (single shot)

ATTACHEMENTS Circuit

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The circuit is a basic MOSFET H-Bridge. When ON, The MOSFET QM bypass R3 which limits the current through the solenoid during the integrity test. A MCU will drive the MOSFETs with optcouplers (ideally simulated with switches).

Please note that the load is only resistive because I haven't done any investigation to calculate the inductance of the solenoid yet (not specified in datasheets). The gate resistors values can be better defined in order to improve the trade-off between resistor power dissipation and MOSFET turn on/off time. Actual MOSFETs can (and will) be replaced by better suited and cheaper MOSFETs.

Plot

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The plot shows the MOSFETs gate voltage, the current through the load and the H-Bridge voltage during the three steps:

  1. 1ms-2ms: pulse for integrity check 2. 3ms-10ms: R3 bypassing 3. 4ms: solenoid latching 4. 7ms: solenoid unlatching

QUESTION: What is the source of the little "spikes" on the gates voltages of the unused H-Bridge side when the other is switching and what is their impact on the circuit?

Are they caused by a charge current flowing via Ciss and Crss thus generating a voltage drop between source and gate? How to overcome them (capacitor in parallel of source resistor) ?

Any circuit design improvement ideas or other solutions are welcome.

Thank you,

Johann

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Reply to
johsey
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I wasn't able to see those images good enough from that sight but I can only imagine that you're talking about the ringing that takes place on the Gates when being switched too fast due to gate charge and inductance...

If that is the case, you need a higher value gate driving R..

If you're getting roll over on the Slew, then, maybe you have too much R, if a corner is appearing on the skew, then you don't have enough sinking going on the match the skew cycle... etc...

Just a thought..

Reply to
Jamie

inductance...

What I'm talking about is the voltage spikes which occur on the gate of the non-active H-Bridge side when the other side is commutated. The following plot shows the gate voltage of the two high side PMOSFETs:

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At 4 ms, when the second high side MOSFET is commutating, the gate voltage of the other high side MOSFET is dropping by ~2V. This drop can lead to the MOSFET in cutoff region going into resistive region and starting driving current (if Vgs rises to the plateau).

As you suggest, smaller gate resistor values decrease this voltage drop but increase dramatically the power dissipation of the resistors. Is there another solution?

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Reply to
johsey

Hmm. Gate R's should not get hot via a standard size. Increasing the driving Gate R should reduce that effect you are seeing..

Have you tested this circuit into a purely resistive load? You may want to see if induction on the load is playing a part in this. The pulse you are seeing maybe leaching through the MosFet on the drain side, which really isn't a good thing, if you know what I mean but I do think you're just seeing gate ringing..

Reply to
Jamie

Yes, but it depends on the resistor package size.

After a few tests, it seems that increasing the gate resistors doesn't decrease that effect. On the other side, adding small capacitors in parallel to the gate resistor connected to the source decreases this phenomenon.

I only simulated with a resistive load, thus the leak of freewheeling diodes in the circuit.

So, if it is gate ringing, the main "bad effect" that can arise is the high-side MOSFET being activated. Am I right or are there other side effects that can impugn the circuit robustness?

Thank you for your help, Johann

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Reply to
johsey

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