I'm currently designing a circuit which has to drive a latching solenoid. This solenoid is part of a machine and will "lock" a pluggable external device. This circuit must remain low cost but robust too.
The circuit works as following: At the start of the machine, a test is done in order to define if the solenoid has been damaged (open-circuit behavior) and must be replaced. During this test, the solenoid is powered with a voltage < 6V to prevent it to activate and the current through it is measured with a sensing resistor.
After this integrity test, the user can plug the external device into the machine: the solenoid act as a lock under 24V (latching).
The user can unplug the device after its use or if an error occured: the solenoid is unlatched under 24V (reverse voltage).
- ESR = 14.11? * U < 6V (during integrity check) * U = 24V (latch/unlatch) * Pulse Ton >= 1ms (single shot)
ATTACHEMENTS CircuitThe circuit is a basic MOSFET H-Bridge. When ON, The MOSFET QM bypass R3 which limits the current through the solenoid during the integrity test. A MCU will drive the MOSFETs with optcouplers (ideally simulated with switches).
Please note that the load is only resistive because I haven't done any investigation to calculate the inductance of the solenoid yet (not specified in datasheets). The gate resistors values can be better defined in order to improve the trade-off between resistor power dissipation and MOSFET turn on/off time. Actual MOSFETs can (and will) be replaced by better suited and cheaper MOSFETs.
PlotThe plot shows the MOSFETs gate voltage, the current through the load and the H-Bridge voltage during the three steps:
- 1ms-2ms: pulse for integrity check 2. 3ms-10ms: R3 bypassing 3. 4ms: solenoid latching 4. 7ms: solenoid unlatching
QUESTION: What is the source of the little "spikes" on the gates voltages of the unused H-Bridge side when the other is switching and what is their impact on the circuit?
Are they caused by a charge current flowing via Ciss and Crss thus generating a voltage drop between source and gate? How to overcome them (capacitor in parallel of source resistor) ?
Any circuit design improvement ideas or other solutions are welcome.
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