Johnson Counter Self Correction

Ahah, one of my favorite subjects - disallowed states in ring counters :-).

For a 5-stage ring counter, all the disallowed sequences walk through "101" or "010" in the inner 3 bits. Just look for one of these (3- input AND gate driven by the right Q and Q-bars), and if you see them, do a master clear.

Tim.

Hello Tim,

Thanks for the quick reply. I realize that most people look for the "010" condition or they have logic within the cell that forces this condition to something else. But what about the condition "0110". What about that illegal state? That condition is illegal too and has to be corrected right? Or am I missing something. For example,

A B C D E

0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 1 1 1 0 1 1 1 1 1 0 1 1 1 1 0 0 1 1 1 0 0 0 1 1 0 0 0 0 1

The state 0110 is not in the above correct states...so does correcting for "010" correct for "0110". If so how so? Also when looking that the spec sheet for a 5 stage Johnson counter (see here:

it doesn't appear that the correct for the "0110" condition. Am I right?

Regards,

Generally ring counters don't have to self-correct immediately on a invalid count... as long as that invalid count eventually leads to a situation where it's turned to a valid count, that generally meets most requirements. Your requirements may be specifically different, though.

In your question about "0110", note that "01100" becomes "10100" becomes "11010" which is then self-corrected by my suggested scheme.

Also note that the internal schematic of the 4017 you point shows a correction scheme that is in detail different than mine, but still eventually corrects all invalid counts. There are lots of different correction schemes available... look in a 70's era logic textbook for some other examples.

Tim.

EVERY state machine design should be able to recover from being in ANY invalid/illegal/unused state. How fast it needs to recover and the complexity of the system depends on your design needs. If you can get into an illegal state and not get back to legal states in the time/clocks you require, you're not done. mike

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Return address is VALID!

here:

it

Things like this are the reason I like "state transition tables"; see

If you try to skip anything there is a big blank square facing you. Enforced thoroughness is good in design.

RayR

here:

it

It certainly helps mediocre engineers.

Have you seen the complexity of the PCI state machines?