The Generic PMOS fet does not conduct when I tried it. When I tried a some specific fet it worked. The supply voltage is large in case the fet is lazy, but no, the problem seems to be in the model. I wanted to play with a circuit from an old Application note. I replaced PNP power Bipolar with a fet. It did not work with plain PMOS. Here is the circuit, if you want to know. It is AN10739 from NXP. The fet is drawn a bit untidily. I tried to reverse it, in case I had made a mistake there. (Models do not break when you connect them wrong way. :). Version 4 SHEET 1 1032 680 WIRE 160 -272 48 -272 WIRE 304 -272 160 -272 WIRE 544 -272 304 -272 WIRE 544 -240 544 -272 WIRE 576 -160 544 -160 WIRE 304 -144 304 -272 WIRE 464 -96 368 -96 WIRE 576 -96 576 -160 WIRE 576 -96 544 -96 WIRE 720 -96 576 -96 WIRE 160 -64 160 -272 WIRE 688 -16 624 -16 WIRE 720 -16 720 -96 WIRE 800 -16 720 -16 WIRE 688 0 688 -16 WIRE 160 16 112 16 WIRE 304 16 304 -48 WIRE 304 16 256 16 WIRE 576 16 304 16 WIRE 576 80 576 16 WIRE 640 80 576 80 WIRE 800 96 800 -16 WIRE 800 96 688 96 WIRE 48 112 48 -272 WIRE 256 112 256 16 WIRE 432 112 384 112 WIRE 528 112 432 112 WIRE 528 128 528 112 WIRE 624 128 624 -16 WIRE 624 128 528 128 WIRE 112 160 112 16 WIRE 192 160 176 160 WIRE 432 160 432 112 WIRE 528 224 528 128 WIRE 608 224 528 224 WIRE 768 224 688 224 WIRE 864 224 768 224 WIRE 864 240 864 224 WIRE 256 288 256 208 WIRE 768 320 768 224 WIRE 864 352 864 304 WIRE 112 400 112 160 WIRE 384 400 384 112 WIRE 384 400 112 400 WIRE 48 448 48 192 WIRE 256 448 256 368 WIRE 256 448 48 448 WIRE 432 448 432 224 WIRE 432 448 256 448 WIRE 768 448 768 384 WIRE 768 448 432 448 WIRE 864 448 864 416 WIRE 864 448 768 448 WIRE 432 480 432 448 FLAG 432 480 0 SYMBOL voltage 48 96 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V1 SYMATTR Value 20 SYMBOL npn 192 112 R0 SYMATTR InstName Q1 SYMBOL pnp 368 -48 R180 SYMATTR InstName Q2 SYMBOL ind 704 208 R90 WINDOW 0 5 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName L1...

As you say, "When I tried a some [sic erat scriptum] specific fet it worked." You've answered your own question. LTspice is notorious for having LTspice-specific models tweaked with special effects to make LTspice look super speedy. I'd do two things, avoid LTspice-specific models and be sure to set solver to "Alternate". Make that _three_ things... treat LTspice XVII with caution until it is completely debugged. Did you try your circuit on LTspice IV? [snip] Complete schematic at... Message-ID: ...Jim Thompson -- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | STV, Queen Creek, AZ 85142 Skype: skypeanalog | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at | 1962 | I'm looking for work... see my website. Thinking...

Is there something wrong with PMOS model in the LTSpice XVII?

Jan 20, 2017 83 Replies

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Tim Williams 9 years ago

"Jim Thompson" wrote in message news: snipped-for-privacy@4ax.com...

Well, that's what the existing one does, in a sense, as I understand it. (You charge up a nonlinear capacitor, and it discharges on reverse. Turn-off is "triggered" when the excess capacitance becomes small enough not to care.)

(Huh...Also, you should know better than to use words like "trigger", Mr. all-continuous-derivatives!)

But that doesn't capture dynamic voltages (namely, the transport stuff Phil is concerned with), which has a more inductive aspect, but a non-conservative (dissipative, lossy) one.

*Shrug*, I always put an R||L in series with the thing, approximating the datasheet's spec (when provided), and that looked right enough. The curve isn't actually linear, but usually sub-linear... almost sqrt(dI/dt), even (ta-da, diffusion magic!). But a linear approximation is more than good enough for a switching supply, where the dI/dt is well defined, consistent and modest.

Tim

Seven Transistor Labs, LLC Electrical Engineering Consultation and Contract Design Website: http://seventransistorlabs.com

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Tim Williams 9 years ago

Well, I wouldn't, but not because of mathematical reasons, but practical ones.

There's little point in modeling an SRD, because I wouldn't expect one to actually be well enough specified to match its model, anyway. You're also talking bandwidths where you need a full E&M model of the circuit, which means you need to lay it out first. Catch-22.

An expensive Catch-22 at that -- once you've mortgaged half of your house to buy the Ansys tool chain!

C'mon Phil, stop sucking on margaritas and kicking sand (by which I mean, trivially pathological cases) in our faces. ;)

A much more practical case for diode modeling: switching supply rectification and snubbing. I've yet to build one where the diodes exhibited snap recovery. The V, I and t are all very well constrained in this case. That's with V and I bounded by datasheet limits (Vrrm and Isurge), and dI/dt maybe 10 A/ns worst case. Oh, and say it's pretty gross, like 20% accuracy.

Is this proscribed well enough now? What's the Big-Oh on the number of internal states?

Tim

Seven Transistor Labs, LLC Electrical Engineering Consultation and Contract Design Website: http://seventransistorlabs.com

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Jim Thompson 9 years ago

The nonlinear capacitor is the key

Easy enough as well.

Indeed. I don't know why Phil got a hair so far up his butt he can't retrieve it. I guess it's the old adage, don't ever try to tell a PhD he's wrong ;-) ...Jim Thompson

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LM 9 years ago

I have now simulated two designs from two earlier writers. They both work. But when looking for a way to attach Star-leds, I found led-supplies which are cheaper, smaller and better than what I was building. I of course new that this is the way it is put it is still frustrating.

After I have attached the leds I'll start building the switcher.

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