Is a Gray code counter more energy efficient?

If I understand him right (enough), then actually he doesn't. "Fractional state" is the whole point of random counters, among others. You can have a smaller state than required by the fully accurate approach to be about right most of the time (statistically).

But I can see no advantages of these techniques in this particular application: dividing by 2^N is so easy.

Best regards, Piotr

That's not true, as pointed out by Rick, but how minimal is minimal? RV3028 needs 48nA wile being significantly more complex than a simple

Best regards, Piotr

Three lines and only four insults. Ricky is off his form.

Some flops use about the same power whether they change state or not. Most, probably.

Quite possibly, but if the part's current consumption is capped at 46nA, would you even care what's inside? Even the CeraCharge's 100uAh capacity is infinite to the first-order approximation.

Best regards, Piotr

None, actually; a flipflop that changes state, without holding a memory of its previous state, takes an irreversible step. Irreversibility implies entropy, thus energy is lost to heat.

Huh... So now it's perfectly clear, that Larkin considers to be an insult, any correction or comment on a technical issue. I certainly should not be surprised by that, but this is so perfectly clear this time. When the comments are directed to Larkin, he probably considers a correction to be the supreme insult.

Depending on what they are driving. You can't just count the power in the gates themselves. The output loads are the majority of the power consumption.

It wouldn't shock me if ECL, especially the eclips parts, use less power when they are clocked hard.

But I did say "about the same power", which doesn't violate any basic principles.

That seems a bit unlikely in general, but in this application yes.

The average power used for changing states of a divide by 2^N chain is typically only about twice what it would be for one of them. Peak consumption N x when all ones to zero rolls over.

Plus N x whatever standing current each flip-flop requires to function. At such very low clock rates I expect the quiescent current is quite a bit bigger than the total current used to change states.

If they were clocked at >10MHz then it might be a different story.

And that is part of the difference between a generic divide by 2^N chip with every output available buffered to an external pin and a custom watch chip where only 1Hz pulse has any connection to the outside world.

How do you know this? Dynamic power dissipation is a property that is very sensitive to implementation.

Again, how do you know this? Again, static power is very sensitive to implementation.

No one has said anything about whether this is being designed from a custom chip or relays.

This is all a thought project, which has never been defined, except for wanting to do something similar to some fancy watch.

I vote for relay logic and a 1 Hz crystal.

Oh, I realize the Landauer effect isn't very large; still, entropy IS a basic principle.

I guess future computers could be cooled. That makes sense: we cool RF gadgets to reduce their noise figures.

Because unless the chip designers are complete morons they won't allow both the FETs to be biassed to conduct hard simultaneously. The typical cost per 0-1-0 transition is the same although there might be some slight asymmetry between 0-1 and 1-0 transitions.

The simple rule is that if it costs x to change state then each change of state will slightly affect the current consumption by adding x. The rest is simple mathematics of dividing by 2.

But for any given implementation the current drawn by a D flip-flop is going to be about the same value y. If there are N of them that is N*y.

I suppose there might be a slight difference due to packaging overhead for any given N if they are available 1, 2, 4 or 8 to a chip.

That might make it a little difficult to wear on a wrist.

I recall one of the world's top experimentalists showing off his brand new Sinclair matchbox sized digital watch in the mid 70's - he was very proud of it. (at the time it was quite amazing for the price)

It would appear that you are not familiar with static power consumption. No? Add a term Pstatic to each of your power calculations, and the ratio of the two are now dependent on the relative size of the static and dynamic power.

As I've mentioned many times in this discussion, there's also the issue of driving loads, both internal and external to the device. Without considering that as well, your figures are meaningless.

Or the entire design on a chip.

This is the bit I was asking about though. Until someone specifies the details of implementation, you don't know anything about this.

Again, that depends on the technology used. They can integrate relays on ICs now.

The energy lost during a full cycle is directly proportional to the load capacitance and the Vdd squared. The power dissipation depends how often these transitions occur.

CMOS gates have power dissipation in the nA / nW class at 5 V.

The 4020A ripple counter has quiscant power is in hundreds of nW, while clocked at 32 kHz the consumption is about 100 times larger. so why bother with the static power dissipation. There are also intermediate stage outputs, adding the capacitance and loading and power consumption.

The consumption of Vdd=1.5 V of a watch ripple counter is even less. especially if there are no intermediate outputs at the higher frequencies.