Interesting First Cut at Spice Modeling of TLP191B

Datasheet comparison now added. ...Jim Thompson

-- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85142 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at

You may have a typo on your pdf formula. Looks like E_E1 N_1 N_2 VALUE { V(OC)/2*TANH(1*(V_IM1)-1u) }

I think you meant the current THROUGH V_IM1 E_E1 N_1 N_2 VALUE { V(OC)/2*TANH(I(V_IM1)-1u) }

I converted your netlist to be LTspice compatible for you to add to your pdf?

.options ITL3 generated an error, so commented it out, don't know the significance.

Tried to preserve your nomenclature as much as possible: [might have a wrap around in there, so watch out]

TLP191B.asc

Version 4 SHEET 1 27404 680 WIRE -208 -800 -240 -800 WIRE -240 -784 -240 -800 WIRE -208 -768 -208 -800 WIRE -208 -672 -208 -688 WIRE 272 -672 -208 -672 WIRE 656 -672 272 -672 WIRE 672 -672 656 -672 WIRE -208 -576 -208 -672 WIRE 272 -528 272 -672 WIRE -448 -512 -480 -512 WIRE 224 -512 160 -512 WIRE -480 -496 -480 -512 WIRE -448 -480 -448 -512 WIRE -256 -480 -272 -480 WIRE -208 -480 -208 -496 WIRE -208 -480 -256 -480 WIRE -208 -464 -208 -480 WIRE 224 -464 208 -464 WIRE 208 -448 208 -464 WIRE 160 -416 160 -512 WIRE 272 -416 272 -448 WIRE 272 -416 160 -416 WIRE 352 -416 272 -416 WIRE 368 -416 352 -416 WIRE 272 -384 272 -416 WIRE -512 -368 -528 -368 WIRE -448 -368 -448 -400 WIRE -448 -368 -512 -368 WIRE -256 -368 -272 -368 WIRE -208 -368 -208 -384 WIRE -208 -368 -256 -368 WIRE -448 -336 -448 -368 WIRE -208 -336 -208 -368 WIRE 272 -304 272 -320 WIRE -448 -240 -448 -256 WIRE -208 -240 -208 -256 FLAG 656 -672 OC FLAG 352 -416 n3 FLAG -512 -368 n4 FLAG -208 -240 0 FLAG 272 -304 0 FLAG -480 -496 0 FLAG -240 -784 0 FLAG -448 -240 0 FLAG 208 -448 0 FLAG -256 -480 n1 FLAG -256 -368 n2 SYMBOL e 272 -544 R0 SYMATTR InstName E2 SYMATTR Value 16 SYMBOL res -224 -592 R0 SYMATTR InstName R_R1 SYMATTR Value 1MEG SYMBOL diode 256 -384 R0 SYMATTR InstName D1 SYMBOL voltage -208 -352 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName Vim1 SYMATTR Value 0 SYMBOL voltage -448 -352 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName VF1 SYMATTR Value 0 SYMBOL bv -208 -480 R0 SYMATTR InstName B_E1 SYMATTR Value V=VALUE( V(OC), I( Vim1) ) SYMBOL current -448 -480 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName Iphoto SYMATTR Value 0 SYMBOL bi -208 -768 R0 SYMATTR InstName B_F1 SYMATTR Value I=F(I(VF1)) TEXT 792 -360 Left 2 !.func VALUE(x,y) { x/2*TANH(y-1e-6) } TEXT 792 -288 Left 2 !.MODEL D D( IS=5f) TEXT 792 -576 Left 2 !.DC LIN Iphoto 1mA 50mA 1uA\n.OPTIONS ITL1=1500\n.OPTIONS ITL2=2000\n*.OPTIONS ITL3=1000\n.OPTIONS STEPGMIN\n.STEP TEMP LIST 25 55 85\n.OP TEXT 792 -320 Left 2 !.func F(x) {x/1000}

Tanh very useful. However... I haven't run your model, but it looks like you have omitted input diode modelling. The clue is that I don't see any Diode model with N !=1

I did this model for a H11FXM opto a while back. Matches DC curves very well.

.SUBCKT h11fxm_XN 1 2 3 4

• B1 3 4 i=0.04*tanh(20*V(3,4))*I(V1) D1 1 5 DMod V1 5 2 DC 0 c1 3 4 10p c2 1 3 0.2p c3 2 4 0.2p .model DMod D(is=1p Rs=3 CJO=50p Tt=10n Bv=50 Ibv=0 N=2.15) .ENDS

Kevin Aylward B.Sc.

Thanks, I'll check that out. An additional tool I need to devise is one that takes my netlist and changes additional subcircuit calls to their text content. Otherwise, as I build models, the library calls would be terrible for users.

...Jim Thompson

Thanks, Kevin, I'll try that out.

...Jim Thompson

Here's a quick sim I did of an optocoupler with its output clamped to make it faster. I hacked an LT Spice library part to sim the Avago coupler with variable CTR. It matches the hardware behavior pretty well.

That particular run is a sweep to determine the voltage threshold.

TLP191B_Subcircuit.pdf

is now available on the Device Models & Subcircuits page of my website. ...Jim Thompson

-- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85142 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at

Not sure if I understand you correctly.

In SuperSpice, .subckt txt models can be all automated via schematic drawing and button presses.

Typically I will generate various behavioural level schematics in a hierarchy and do a "Create .subckt from schematic" to get the models. I then attach those models to symbols and make a top schematic using those sub models. I then create a wrapping subckt from the top. It is far easier to debug schematics than text files. I even have a suite of behaviour digital logic, including d-types etc, using only tanh() equations!

e.g. My CurrentModeController is below for illustration. This model should run in any Spice3/XSpice. SS can also automatically insert voltage sources in the pins so that currents can be probed.

.SUBCKT CurrentModeController_XN eap ean csp !3_csn !4_cmout !5_cmvcc !6_cmvee r rc c ain anegin aout

• _SS_Symbol [Functional.ssm] [CurrentModeController] V!6 !6_cmvee cmvee 0 V!5 !5_cmvcc cmvcc 0 V!4 !4_cmout cmout 0 V!3 !3_csn csn 0

• eap -> error amp positive input -> connect to vref
• ean ->error amp negative input -> connect to supply output feedback
• current feedback in csp and csn the current fb amp has a fixed gain of

• csp -> current sense input, positive
• csn -> current sense input, negative
• out -> main switch driver output
• pvcc, nvee -> supply voltage
• r , rc, c oscillator, f =approx 1/RC. Connect r to r and rc and c to c and rc
• model should work up to 10Mhz unmodified
• (c) Kevin Aylward 2002 - All rights reserved, snipped-for-privacy@anasoft.co.uk
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• This model may be freely copied and used, provided this copyright notice is included

• .SUBCKT SuperSpiceSchmitt_XN !0_negschimttin schmittout posv negv b1 1 2 v=v(posv,negv)*tanh(0.1+v(posin,!0_negschimttin)/v(posv,negv)*2e3)/2 c1 3 2 15.9p r1 1 3 100 b2 schmittout 2 v=v(3,2) e2 2 negv posv negv 0.5 e3 posin 2 schmittout 2 0.5 .ends
• .MODEL SMPSSwitchConverge_XN sw(ron=1m roff=100Meg vt=0 vh=1m)
• .MODEL SMPSClamp1_XN d(bv=1 cjo=1p rs=1m)
• .SUBCKT ANOR1_XN !0_in1 in2 out p_vdd p_vss m1 out in2 p_vss p_vss nmos1 L=1u W=50u m2 out !0_in1 p_vss p_vss nmos1 L=1u W=50u m3 3 in2 p_vdd p_vdd pmos1 L=1u W=100u m4 out !0_in1 3 p_vdd pmos1 L=1u W=100u .model nmos1 nmos(level=2 vto=700m kp=100u lambda=50m cgso=1n cgdo=1n cgbo=1n cbd=10p cbs=10p) .model pmos1 pmos(level=2 vto=-700m kp=50u lambda=50m cgso=1n cgdo=1n cgbo=1n cbd=10p cbs=10p) .ends
• .SUBCKT SuperSpiceComparitor_XN !0_posin negcompin compout posv negv b1 1 2 v=v(posv,negv)*tanh(v(!0_posin,negcompin)/v(posv,negv)*2e3)/2 c1 3 2 15.9p r1 1 3 100 e1 compout 2 3 2 1 e2 2 negv posv negv 0.5 .ends
• .SUBCKT SuperSpiceAmp_XN !0_posin negampin ampout posv negv b1 1 2 v=v(posv,negv)*tanh(v(!0_posin,negampin)/v(posv,negv)*2e4)/2 c1 3 2 15.9p r1 1 3 100k e1 ampout 2 3 2 1 e2 2 negv posv negv 0.5 .ends
• .MODEL SMPSClamp2_XN d(bv=100 cjo=1p)
• .ENDS

Regards

Kevin Aylward B.Sc.

You missed my point, or, more likely, I didn't explain it well. I have no problem nesting, I just don't like it. For a specific sub-subcircuit I want the PARAMS filled in, and no calls.

Part of the reason is to conceal my techniques >:-} ...Jim Thompson