[LTSPICE] crystal circuit modeling settling time and certainty

phase

start

out

but

Hi Thanks again, im using step of 100ns and start stop of .045/.05 and found it settles down ok if i reduce the q to 1000, it will do for now to see what diference circuit changes make anyway, the output seems to be proportional to Q (as would be expected).

This takes significant amount of time on an amd64 3200, from your information i would need to increase the amount of points by about 20+ however i have often found before that it runs out of memory quite quickly if i use small step size and long sim time (and i lose any changes), i will now try your other sugestions tho, i think trying to set .ic might be a bit hit and miss but il try it anyway.

is there a way to specify nodes to always be used in the FFT ?

Colin =^.^=

spread

this

further

found

proportional

quickly

hi, sorry what i meant was when i run the transient simulation it remembers what signals i used last time and uses them again but when i produce an fft from that trace it never seems to remember wich signals i used before, and it seems to ask me twice too. I asumed '.save ...' was just to save space, although it gives me fewer signals to select from i still defualts to not all or none selected.

yes i think the athlon64 is quite fast even for 32 bit apps, i got it not that long ago and was looking to see if its worth upgrading yet, the dual core chips look interesting but ive usualy only upgraded if i can get at least a 3x improvement in speed for a good price. what would be interesting tho is to see how fast it performs in full 64 bit mode.

Colin =^.^=

"colin" schrieb im Newsbeitrag news:acyte.21413$ snipped-for-privacy@newsfe2-win.ntli.net...

Hello Colin,

The settling time is about 0.35/(f0/Q). This results in a settling time in the range of 0.1s to 90% of the final value (F0=100kHz, BW=f0/Q=5Hz).

I have summarized my ideas about crystal circuit simulation from previous postings to user groups. Maybe not all are necessary or helpful in your case.

1. Switch off the data compression to achieve "clean" signals. ..options plotwinsize=0

1. The maxiumim timestep in ".tran" have to be set to about

1/(1000*f0) or less. Of course this can become a nightmare in terms of simulation time and size of the output file

1. I recommend to use the ".save .." command to limit the number of saved node voltages.

2. Try to precharge the important nodes with ".ic" to reduce startup settling time.

1. Switch off marching waveforms to stop graphic output during simulation. ..options nomarch

2. Use a fast PC. The best choice is PC with a 4GHz AMD Athlon64. I proved that with a 3.4GHz P4 and a 3.5GHz+ Athlon64(Venice). The Athlon64 has been 25% faster.

Best regards, Helmut

"colin" schrieb im Newsbeitrag news:FCEte.1986$ snipped-for-privacy@newsfe1-win.ntli.net...

Hello Colin,

I don't really understand your last question.

What's about

..save V(sig1) V(sig2) V(sig3) ... I(out) ...

Only specify the nodes you need.

You have at least a fast PC. Belive me a P4 with 3.4GHz is slower than your PC when running LTspice. -> No need to upgrade! You are already on the edge.

It's not uncommon to run into 1GByte with the file size of the ".raw"-file. If that happens with your "final" simulation and you have many traces saved, then it may be worth to convert the ".raw"-file to "fast format".

File -> Convert to fast Access

This conversion can take as long as the simulation. It simply changes the order of the saved data to have faster access to the required trace.

Best regards, Helmut

"colin" schrieb im Newsbeitrag news:OpFte.2135$ snipped-for-privacy@newsfe1-win.ntli.net...

Hello Colin,

Please plot the signals from which you want to have a FFT. Then save this plot settings to a file for later use. Now go to FFT. -> The signals from the plot are already selected in the first selection box. Ok, in the second you have to mark it.

The plot settings have to be reloaded after every simulation, but this reload could be assigned to a hot-key.

There is no hope that a dual CPU gives any advantage. Somebody tested a few weeks ago on a dual Intel XEON. The result was very disappointing. Zero perecent advantage over a similar single CPU system. Only the output window can run in parallel, but this is only a very few percent of the total system load. If you switch off marching waveforms, then the output window doesn't take any processing power too.

Mike has compiled one time a year a P4 optimized version in the past. He got about 20%? speed improvement. It's just too much work for him to support two versions. Write him a nice letter and ask for a 64bit version if you have a 64bit WIN-XP.

Best regards, Helmut

Trying to ".IC" within the crystal will probably be difficult. If I'm not trying to prove startup, I simply put an atrocious skewing .IC within the oscillator itself, or use a "kick-start" current pulse.

On the other hand, if you're simply .AC simulating a crystal filter, you just need to force very small frequency steps... like Fo/Q/100, if you want to really have a handle on the transitions.

...Jim Thompson

--
|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
|  Analog/Mixed-Signal ASIC\'s and Discrete Systems  |    manus    |
|  Phoenix, Arizona            Voice:(480)460-2350  |             |
|  E-mail Address at Website     Fax:(480)460-2142  |  Brass Rat  |
|       http://www.analog-innovations.com           |    1962     |
             
I love to cook with wine.      Sometimes I even put it in the food.

Hi as you sugest im trying to set up initial conditions with .ic for my crystal, I want to specify the current but as i can only do this for an inductor how do i reference the equivalent inductor inside the crystal circuit or any other component for that matter inside a subckt (within a subckt)? i cant seem to find this in the help file.

I know this is actualy an ordinary capacitor (and i have set it inside a subckt to calculate the corect component values from the freq/q etc) so does this mean it is inacesible ?

I gues i can either add an inductor in series with it or expand the capacitor parasitics into the subckt, or try to make it zero current at t=0 but this would complicate things a bit. (especialy as i have 2 crystals)

Colin =^.^=

does

t=0

Thanks, however im trying to model a crystal used as a narrowband filter for phase demodulation, and although a frequency responce analysis is usefull I need to look at the .TR too, it takes about 100ms to settle down, wich can take a long time to run. I tried about 10kv acros wich kinda works although it takes quite a while for this voltage to decay too.

Colin =^.^=

phase

(q=20000)

with

Well I've managed to come up with a reasonably consistent set of results now, for a 1mhz signal modulated by +-20ns at 20hz ... if I calculate the output from the phase shift alone compared to the original source I estimate 14mv output, when I calulate the phase shift derived from the bode plot I estimate 10mv output, when I run the transient analysis I first got 3mv, wich then increased to

17mv when I reduced the timestep considerably.

Although the real modulation level is several orders of magnitude lower, so I'm stil looking at signal ridicoulsly lower than the noise floor ...

Colin =^.^=