Input stage for VHF frequency counter in an FPGA?

cs_posting · 2006-02-23T03:01:44+00:00

The other day I found myself needing a short gate time ~200 mhzfrequency counter for an automated test, and since I had an FPGA boardon hand I whipped one up quickly. Getting it reading and reporting tomy computer was the easy part.Ah, the input stage....I've got about 4dBm of RF into 50 ohms to play with - about a volt p-por a little more if it's high-Z. The output of the device under testhas a transformer and then a series cap to create an unbalanced output.I did something ugly with a 3.3v cmos 7406 varient and a feedbackresistor, which works well enough to get an accurate reading on oneversion of the device under test, but not on the other (both have beenverified with real test equipment) It also tends to self-oscillatewith no input...What would be the right way to do this using on hand parts, such asabused logic, little 1:1 or 2:1 RF transformers, etc? One idea is touse another gate with a feedback resistor and cap to ground in the hopeof establishing the threshold level, and then using a transformer toswing another input above and below this. Most parts on hand are SMD -which means dead bug construction in SOIC scale under the maginifier -discourages extensive experimentation.Why do most abuse-of-logic RF applications seem to use NAND gatesrather than inverters? From a digital perspective NAND gates are auniversal element, but once you tie their inputs together, is theresomething to be gained from having two inputs in parallel?Is there a way to use a differential input configuration on an FPGA toinput a balanced RF signal directly? Theoretically this should be anFPGA clock input... The device in use currently is an Altera StratixII, but a Xilinx S3 kit is available.If ordering things, what would be a good default low supply voltageHF/VHF gain component to have on hand? I seem to recall lots oflast-millenium ham designs using the MC1350P video IF amp, but whatwould make sense today?

Feb 23, 2006 20 Replies

Rate this thread:

cs_posting 20 years ago

Good point to keep in mind. In this case though it's all 3.3v families, and LVTTL seems to have nearly the same Vih/Vil spec as LVCMOS. The part is spec'd with minimum Voh of 2.4v.

Vote

Join the Discussion

Have something to add? Share your thoughts — no account required.

Didn't find your answer?

Ask the community — no account required

Input stage for VHF frequency counter in an FPGA?

Related discussions