Hot plugging serial EEPROM

Isn't the usual game to have one short (length) pin in the connector that controls activation? ...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    | 
| San Tan Valley, AZ 85142   Skype: Contacts Only  |             | 
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  | 
| E-mail Icon at http://www.analog-innovations.com |    1962     | 

Worst President EVER declares, "Donald Trump is not equipped to  
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Usually, yes, but that's not possible since I'd have to use an off-the-shelf connector like a d-sub.

Definitely have diodes from the data/clock connector pins to Vdd and ground. Also a capacitor Vdd-Gnd of 10nF to 100nF. Then series resistors in the data/clock lines, between those prot diodes and eeprom chip. Those resistors should be low enough to not impair i/o but high enough to prevent chip latch-up if hot plugging results in unfortunate power sequencing. At a guess 100R to 470R ? The diodes will help catch esd and the capacitor will stop Vdd rising during an esd event. If you want also add small capacitors from data/clock to ground, at the chip pins so they form RC filter with the series resistors. Say 15pF to 100pF to slow esd edges enough for the on-chip protection networks to have a chance. Also consider tying the connector shell to ground as most of the time the shell will be the first thing to make contact.

piglet

How about requiring a pin from each _end_ connecting to initiate activation? ...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    | 
| San Tan Valley, AZ 85142   Skype: Contacts Only  |             | 
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  | 
| E-mail Icon at http://www.analog-innovations.com |    1962     | 
              
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to contain a serial NVRAM device to hold information about what is attached to the connector. Very little storage will be needed, maybe 64 bytes or s o. This connector will be hot-plugged into a product which access the NVRA M.

Well, mass-produced USB devices, and their plug arrangements and sockets, d o this all the time. Does it have to be a symmetric connector like D-sub? Could you use, for instance, SD? Micro-SD? Staggered-pin standard socket solutions are hot-plug ready and ubiquitous.

Ooh, that'd work nice.

I was thinking a power pin to the connector, and a "power good" from it, possibly with a delay circuit so that you _know_ it's good.

I could see it causing problems if you had more than one device on your I2C bus -- you'd want to think about that if you did.

--

Tim Wescott 
Wescott Design Services 
http://www.wescottdesign.com

If the d-sub shells are all ground, the shells will (usually) connect before the pins, which is the first level of protection.

I'd add a 1K resistor in the chip clock, cs, miso, and mosi pins, one nice little quad pack. Most eeproms have a schmitt on their clock input so won't mind a slow edge.

Do any of the other d-sub pins have giant voltages?

--

John Larkin         Highland Technology, Inc 
picosecond timing   precision measurement  

jlarkin att highlandtechnology dott com 
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need to contain a serial NVRAM device to hold information about what is attached to the connector. Very little storage will be needed, maybe 64 bytes or so. This connector will be hot-plugged into a product which access the NVRAM.

hotplugging, with each connection (power and data) making contact in an unpredictable order? I've considered running diodes from each signal line to power and ground in the case that signal lines make contact first, but the entire situation leaves me a bit uncomfortable.

haven't used these before, not that I can't figure it out. Anyone have experience with this type of situation?

On the host side drive SCLK, CS and SDI through a buffer (tri-state) with all the proper ESD on the connector side. Buffer SDO from the EEPROM with a tri-state buffer, again with your ESD on the connector side. Current limit V+ with your fav load switch or other means.

On the device side, ESD all the lines and use a RC delay as an enable input back to the host buffer. Find a EEPROM with enable and hold the chip disabled for the RC delay. Your uC can use the enable to know the device is plugged in (or at least think it is plugged in).

Another way is to use RS232 drivers/receivers that can withstand a direct short to either V+ or GND on the outputs and drive your SPI signals through that. But you gotta watch your SCLK speeds but you probably dont need blazing speed anyway.

--
Chisolm 
Republic of Texas

NXP and others have Hot Swapable I2C bus/SMBbus things.

Otherwise Latch up might be a problem.

Cheers

Obvious solution: use a 1-wire device. It just needs 2 pins: the 1-wire signal and gnd, completely avoiding any pin sequencing issues.

Each 1-wire device has a unique address which can also be used as a serial number for your product.

There are some low cost memories available, designed for (e.g.) printer cartridges. Similar 1-wire EEPROM parts are used in laptop "brick" power supplies from e.g. Dell. Apple use a 1-wire device in their power supply magsafe connector (it's actually in the connector, not the brick), but it's just a GPIO chip that drives the charging LED and contains no memory (all the information about the power supply is contained in the 1-wire address).

The bus master could be dedicated hardware (e.g. an I2C to 1-wire bridge) or you can bit-bash it on a GPIO pin. The protocol requires tight control of timing though. There are two timing variants, and your master must using timing appropriate for the slave.

Dunno what OS you're using. The linux driver is called "w1".

These devices are from Maxim. I know what people say about Maxim (and I've been burnt before too) but I've never had a problem sourcing the more popular 1-wire devices.

Regards, Allan

Sometimes resistors are sufficient to code boards or cables if only 24 variants exist.

For I2C EEPROMs i use edge connectors ( picture 8 )

There the pcb could provide short length pins. Hot plugging is not intended, i have not implemented that. I doubt there are problems as the controller portpins do not source enough current for latchup.

Maxim is ok if there is a controller that can do the bit banging in assembler.

MfG JRD

This is the conclusion I've been coming to. They even have superb ESD ratings. I've found some C source written I could use to get up and going faster.

To answer some other questions others have asked: we need about 40 connections and it's low voltage. And not using an OS, it's running off a small micro.

I've had success using this eight channel part as a bus master: One of its advantages is that it takes care of the details of the timing, relieving your software of that burden.

In my application I had only one slave per bus, so I can't comment on the fanout limitations one meets in practice.

BTW, the bus is usually idle (at +3.3V) and it won't detect that your device has been unplugged unless your software polls the slaves. For that reason, I recommend having an additional pin on your connector to indicate "presence".

Regards, Allan

On Fri, 6 May 2016 20:00:24 +0100, piglet Gave us: snip

Well hot plugging an EEPROM worked in "Real Genius". ;-)

Re-targeted the computer and set the laser up to burn itself up after one shot. And the saboteurs didn't even get caught. Hehehehe.

I2C and SMB bus have recognized this hazard for a long time, particularly where live battery insertions/withrawals occur through unsequenced hardware.

Single or multiple buffers/inverters with input supply immunity are one solution.

Using a valid ground connection to switch the supply rail is another.

RL

Put power and ground on the corner pins in an alternating fashion. That should help.

What do they do with the EEPROMs in VGA monitors? I guess you aren't supposed to hot-plug those VGA cables but everyone does when giving presentations on video projectors.

The issue of power pin/logic hot swap sequencing cannot be ameliorated using a logical process requiring established power in the unpowered plug-in assy. The worst-case assumption for indeterminate sequencing is +V first contact, gnd last.

Intermediate contacts all see voltages pulled hard below 'local gnd'......and local ground will be at the +V potential through uncharged decoupling caps to pull incoming host signals to that rail.

Ground first contact still requires signal pin immunity above local

+V.

Correctly sequenced pin mating may still require pre-charging or source decoupling, so as to avoid pin damage or transient overloading of the source.

Signal pins (external and internal) need to be immune to signal level loading to the external rails, while internal rails are being established.

Even local supply rail faults applied to a self-contained assembly can result in corruption of common erasible memory contents, regardless of whether the hardware remains physically undamaged. It's one of the hardest sells - placing such components within the power supply itself without adequate allowances for local internal component supply susceptibility - as recovery from a single fault may not be consistently demonstrated.

RL

Apart from device id and user settings, I'm not sure how important eeprom is in a monitor, but that info is via I2C, for which protection can be achieved, with care. Remember that I2C is a low frequency open drain/collector signal.

Remember also that monitors have their own power supply, so this question is different than the OP's. The I2C communication here doesn't include a power transfer. Power sequencing issues occur equally in both directions - possible damage to the computer and the monitor - however one does not provide power to the other.

As you can't assume that power is ever applied to interconnected devices in a specific sequence, physical protection is normally built in for the unpowered condition of either side of hardware interconnection. Examine the schematic and you'll see zeners and series limiters referenced to internal supply rails on both sides of the interface.

None anticipate hotswapping of connectors, but the protection for supply sequencing on the (all) signal lines will serve the same function in a lot of situations. At the same time, most operating manuals do not advise removing or inserting VGA while power is applied on either side, as a CYA provision.

RL