fried VME modules

Jun 05, 2021 Last reply: 5 years ago 180 Replies

pretty much what is on the usually ultracap protector/balancers

formatting link
though I think they usually us a power BJT

You should be able to just click and see it. Here's a different option:

formatting link
and the ugly that we need to clamp:

formatting link
Oh all right, I'll use a depletion fet.

I claim that 50% of electronic design is packaging and the other 70% is thermal.

Sure, either would probably work. Ideally the rail will never get past

5.5 V, in which case the original version is fine too, but it's hard to tell for sure without having a PSU to play with.

Cheers

Phil Hobbs

It's too bad there's only 2 or 3 power supply factories in the world and the customer can't start with clean power.

retardation like this is why companies get hacked all the time.

We tend to put the real AC line switch on the back, as part of the AC inlet/EMI thing, and put a "soft" switch on the front panel. That gives us more control.

That sounds reasonable. I take it you're not using the cheapest alibaba power supplies either from the photos you post.

Your client with the car battery charger for power supplies on the other hand does thing differently.

We use a lot of Mean Well supplies. They have been very good.

+1.

Our standard wall wart is SL Power's ME10A2403B01, which is terrific.

Cheers

Phil Hobbs

We use a similar part, Phihong I think. It has a screw-locking barrel connector and our PCBs have a corresponding threaded mate.

Isn't that exactly the sketch I posted last week?

formatting link

piglet

Keeping the fixed LM4040-5 I reckon if JL omits the 10k R5 and replaces D3A BAT74 with a 1k-ish resistor then drive to the PNP is improved, the penalty is a slightly higher clamp voltage closer to 6V.

piglet

Here's a plot of Vgs vs Ids for HUF75652, as used in the simplest pulser from the Rowland Inst. (Winfield Hill)

formatting link
This used relatively flat Vg to program pulse current levels by modulating gate driver supply voltage, with a 10mR source resistor.

RL

Probably so. I didn't actually look at it.

Cheers

Phil Hobbs

We have some dpak fets in stock that will conduct over 150 amps with

+6 on their gates. In this circuit, they are hard saturated by then, and most of the power dissipation shifts to the twenty 2512 resistors.

formatting link
The X-chapters have some cool graphs of the pulsed-power destruction limits of various resistors.

Hmmm, a fairly simple change to the gate driver circuit could put more than the supply voltage on the gates. Not sure if that would be be a good thing to do.

Pulsing the HUFxxx as power zener (2x1N914s from drain to gate) with 14ms half sine, here's what you'd get.

formatting link
Hope you get a nice reliably-faulty power supply to prove function with.

RL

On further thought I think JL may want to review ditching that diode D3A as I suggested earlier (above) - in my calcs it lowers the clamp voltage enough to potentially activate the clamp at 5.25V which is within VME spec.

piglet

Dropbox is set up to look like an account is required, but if you just dismiss the box, you will see the schematic. The intentionally misleading box is annoying for sure.

Joe Gwinn

My deepest sympathies for the unfortunate screwdriver.

Joe Gwinn

[...]

I would use a TL431. The LM4040 is alright but D3-A and Q1 add tolerance to it and you might still exceed abs max VCC for FPGA or other parts. Some can be like the princess on the pea.

Nashty!

:-)

That would have to be a big old fat one, and wouldn't be very precise.

The remaining 10% is finding good brewpubs and checking their opening hours.

Join the Discussion

Have something to add? Share your thoughts — no account required.

Didn't find your answer?

Ask the community — no account required