Frequency signal multiplier - repost.

In article , Rich Grise wrote: [...]

Or use the flip-flop type phase detector not the XOR one. The 4046 has both types on it.

Or raise the VCO's frequency to 6X the input. like this:

Look here:

formatting link

CD4046 pins used in this design:

Signal In = pin 14

This pin has some bias circuits hooked to it so you can apply a small signal through a capacitor. If your signal is already going from ground to Vcc, just ignore the bias stuff and hook it up.

Internally this signal goes to both phase detectors as the expected "input".

Phase Comparitor feedback in = pin 3

This pin hooks to the output of the divide by 3 (or 6) counter. This is expected to be the "feedback signal".

Phase comparitor 2 out = pin 13

This pin is driven high if the feedback signal is slower than the "input" signal. If the feedback is faster, it is driven low. If it is just right the chip floats the pin.

This normally hooks to an RC low pass filter.

VCO in = pin 9

The voltage on here controls the frequency the (V)oltage (C)ontrolled (O)scillator runs at. A high voltage means faster.

C1A and C1B = pins 6 and 7

You hook a capacitor of many pF between these pins to help set the frequency of the VCO. A bigger capacitor means slower.

R1 = pin 11

Pin needs a resistor to ground. This resistor sets the amount the frequency changes as the "VCO in" is taken fron ground to Vcc.

R2 = pin 12

This pin also gets a resistor to ground, or may be left open. This controls the frequency the VCO runs at when the "VCO in" is at ground. If it is open, the VCO usually just about stops for zero volts.

Page 9 tells you about R1, R2 and C1. Remember the VCO is running at twice (4 times) the output frequency.

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kensmith@rahul.net   forging knowledge
Reply to
Ken Smith
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In article , George Gosbee wrote: [...]

7.5KHz and 7500 rpm don't match up:

7500 RPM * Number_of_cyl / 60Seconds =

You need a flip-flop to know whether this is an even or an odd pulse.

I don't remember what your input pulse looks like. Just for fun, lets assume that it either is or could be cleaned up into a square pulse. I'm thinking like this:

---------- ---------- Input ---------- ------------- ---------- . . . . --- --- --- . Output ---------- ------- ---------- -----------------

Notice how the output gallops. Will this be a problem?

I'm sure others will find something wrong with this but here's my idea:

I call your cleaned up signal "IN"

Even vs odd ckt:

------------ ! CD4013 ! ! ----- ! --!D ! ! IN-----!> ! ! ! Q/!---+--- EVEN to the rest of it -----

See the CD4013's data sheet about reset and set inputs. They need to be grounded. Also ground the unused inputs of the other section.

Was a little while ago circuit

R1 IN ---/\\/\\/---+----- WAS to the rest of it ! --- C1 --- ! GND

Out of pure laziness, I didn't give you actual R and C values. R is going to be 10K .. 100K or so.

The rest of it:

CD4051 -------- EVEN-----!C ! WAS-----!B ! IN-----!A ! ! Y!--------- OUTPUT GND---!X0 ! VCC---!X1 ! VCC---!X2 ! GND---!X3 ! GND---!X4 ! VCC---!X5 ! GND---!X6 ! GND---!X7 ! --------

See the 4051's data sheet for where the "INH", "VCC" and "GND" signals go.

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kensmith@rahul.net   forging knowledge
Reply to
Ken Smith

The 4-0-4V minimum power supply makes things a little tricky. Might try something like this.

100 +Vbatt------+---/\\/\\---+------+----------> Vdd | \\_|_ | 1.8k / 5.1 /_\\ |+ \\ | === / \\_|_ |100uF | 5.1 /_\\ | | | | +----------+------------+----> 0v \\_|_ | | 5.1 /_\\ | ===0.1u | | | GND--------------------+------+-----+----> Vss

Vdd to pins (14) on both chips, plus 10k Fout/2 pullup.

0v to pins (2) and (6) on both chips.

Vss to pins (4),(7),(8),(9) on both chips and 100k bias R's.

And then the F/V, V/F converters like this....

100k Vss 100k (1)---/\\/\\---+----/\\/\\----(1)

Vdd--/\\/\\-----(10)--> Fout/2 10k

Fin, using---->(11) +--(11) Fig 7-1b Vcoupling | (12)---+---+------+ +--(12) | | | | | \\RV1 | | | /50k | | | \\pot | | 2nF=== | | ===470pF | \\270k \\ | | / / | | \\ 300k\\ | | | | | (3)---+---+ +----+--(3) | | 330pF=== ===100pF | | (5)---+ +---(5)

F-V /|\\ V-F /|\\

The output is taken off the Fout/2 to get a nice square wave, so we need Fout = 3 x Fin.

Vcoupling = Fin x 5.1 x (330+12pF) x (270k+RV1).

= Fout x 5.1 x (100+12pF) x (300k).

To get the req'd 3:1 internal F-ratio, RV1 = 33k approx.

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Tony Williams.
Reply to
Tony Williams

Have now solved the original problem with 3 diodes and 1 resistor see, Header -- LPG ecu diode sketch -- in, alt.binaries.schematics.

Thanks for all the help everyone and the lpg now works ok just a little fine tuning to do.

George.

Reply to
George Gosbee

Have now solved the original problem with 3 diodes and 1 resistor see, Header -- LPG ecu diode sketch -- in, alt.binaries.schematics.

Thanks for all the help everyone and the lpg now works ok just a little fine tuning to do.

George.

Reply to
George Gosbee

Have now solved the original problem with 3 diodes and 1 resistor see, Header -- LPG ecu diode sketch -- in, alt.binaries.schematics.

Thanks for all the help everyone and the lpg now works ok just a little fine tuning to do.

George.

Reply to
George Gosbee

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