fast NPN in LT Spice

The pulse stretching happens between the two BFR92 transistors, which act as a classical emitted-coupled monostable, which stretch the input spike out to about 30nsec

Q3 and Q4 just level shift this down to provide an ECL-level output pulse which is also 30nsec wide.

There are other ways of doing this kind of level shifting and you can use faster transistors.

Not one that I made. The BFR92a is just the default broad-band transistor, which is why Jeroen Belleman picked it too.

If they aren't fast enough to get triggered as emitter-coupled monostable by a pulse that is 400psec wide at hallf-maximium voltage of 100mV.

Broad-band transistors will oscillate without a base-stopper of adequate resistance - I tended to end up with resistors between 22R and 33R. There are better solutions, but in the work I did it wasn't worth the trouble of finding them.

Up the gain.

Change the base-stopper resistance.

No model is perfect. If you model something and it seems to work, it's worth putting together a real circuit (which takes longer) and seeing what it actually does.

If it doesn't work, or doesn't work all that well. fiddling with the model may point the way to something that might work better.

I believe that a Spice model should be treated as an engineering document: visible title, author, and correct latest-edit date, and it should be neatly drawn, with coherent comments where appropriate. It should be obvious where the inputs and outputs are, and important nodes should have useful net names.

Versions should be identifiable as such.

A sim should be useful days or years after it's started. We often have a README.txt file alongside the .asc files to explain the situation.

Most amateur Spice sims are messy tangled horrors.

If they are part of production documentation, all this goes without saying.

If we are posting a simple circuit here to make a point, it is less obvious that we need to conform to your production standards.

What I posted was a very simple four transistor circuit - two fast NPNs arranged as an emitter-coupled 30nsec monostable and a slower long-tailed pair level shifter to turn the output into an ECL-level pulse.

Anybody who has done discrete transistor design should have been able to parse it by looking at it.

The only messy object in the diagram was the Spice directive defining the BFR92a Spice model, and the only reason I posted the .asc file was to provide an example of that approach in action.

I've no idea why I put the sim together - it's paired with a bare two-BFR92a emitter coupled monostable sim where the components were strung between +5V and and -5V rails. The real life examples it was probably drawn from had a +5V rail for the old TTL and a -4.5V rail for the old ECL, though I did some work with the Gigabit Logic's GaAs parts that needed two negative rails, -3.3V and -5.2V which was a real pain, but that was just before ECLinPs and if you needed the speed, that was what it took.

You shouldn't have needed a README.txt file to tell you how to parse that circuit.

If you can't parse a circuit diagram, it always looks like a messy tangled horror, and anything complicated always takes a certain amount of inspection before it starts making sense.

If you though that what I posted was a "messy tangled horror" you are at the "cat sat on the mat" level of schematic reading.

It's difficult to isolate a model parameter or product of parameters that predict the performance demonstrated in this simulation.

Oscillators seem to have ( ~ mostly) high Rbb, which is device-specific. . . . but also lower ( 1/100) IKR, which you'd think was irrelevant.

Bf, Tr, Tf and capacitances don't stand out.

I suppose you'd need to look at the numbers separating astable from monostable operation. You wouldn't want an unspecified component characteric to dominate basic circuit function.

RL

You don't get the choice, unless you are in the position of developing a new transistor for a new market.

Most of us are in the position of finding a transistor which we can buy

- preferably off the shelf - which we can use to do a specific job.

The options tend to be pretty restricted. There are a lot fewer broad-band transistors on the market than there used to be.

The manufacturer's Spice model give us the option of modelling a circuit which might work in some version of Spice, and tweaking the circuit to get the simulation to perform our job tolerably well.

We can't sell the simulation - customers want real circuits that work in real life.

That's sort of what I'm talking about. You choose a part, you choose a model, you choose a parameter that allows a model to simulate performance more accurately. You choose a circuit configuration with component values.

From the larger spreadsheet, you see models for 'similar devices varying widely in performance in a particular circuit configuration.

So what is it, in the model, or in the circuit configuration, that allows such a wide variation in performance. What parameter is a true predictor? What weakness in the circuit is the wild card?

Looking for understanding or beneficial increase in knowledge here. Not pushing or pulling the benefits or disadvantages of modeling or breadboarding - already have pretty fixed opinions about that.

RL

You mostly can't chose an EBIC model because the manufacturers treat them as "commercial in confidence".

Gummel-Poon isn't as good, but it's mostly adequate.

Silly question. Gummel-Poon doesn't model inverted bipolar transistor operation particularly well, but if you want anything else you will have measure the device parameters for yourself, and nobody here has ever claimed to have done that.

Do try to understand what practical circuit designers actually do.

I've never seen anybody set up a "spreadsheet" of transistor models.

The process is mostly working out what you can do with what you can get.

The models aren't perfect, and individual devices aren't identical, so coping with production variation is part of the job. Some parts are sorted by the manufacturer after production, which gives you funny-looking parameter distributions.

Some obvious typos showed up, duplicates and variations, derivatives, dated precursors etc.

Depth of parameter assignment, redundant default listings and misinterpreted 'intended to default' values also became apparent.

Some attempt at performance over temperature also shows up in the listing.

I don't think that perfection is attempted; more representation of performance in known physical circuitry or test measurement setups. Test circuitry is sometimes illustrated in, or accompanies the published specification for, the physical product.

The performance in the simulation in question doesn't touch inverted operation, that I can see, but linear operation and ~saturated switching may be. It's not an AC analysis.

RL

Right, I see Q2 normally inverted.

C2 seems unneccessarily loaded.

RL

If you are talking about the .asc file I posted on the 3rd June, Q2 isn't "normally inverted" - its mostly on, and it gets turned off for the 30nsec in which the stretched pulse is being generated. Inverted operation of a bipolar transistor is usually taken to mean running current through them in the opposite direction than is seen in normal operation.

C2 isn't carrying any current worth worrying about. It stabilises the voltage at the base of Q3 against the base current drawn when the output pulse is turned on and turned off, -6.7mA when it is turned on an +2mA when it is turned off, and holds the voltage excursion down to 3.7mV, not that I ever bothered working this out.

If you want to discuss when the circuit does and how it does it, feel free, but this wasn't a good start.

Just returning to this, trying to see what determines the switch from non-switching to astable operation (ECLTN0E - ECLTN0D). Misreading a current and voltage waveform with similar color coding.

Not so much interested in the circuit, as its reaction to model parameters presented by similar devices.

Not Beta, Tr or Tf in this case.

RL

You need to work out how the emitter-couple monostable works.

The Gummel-Poon transistor model keeeps track of the various currents flowing in and out of each transistor junction while this is going on, and subtle differences in the parameter values can give you different currents (and different trajectories)

If you don't know what the circuit is doing, speculation about what the model might be doing it is a bit pointless.

The emitter-coupled monstable isn't well understood here.

This is from the end of a long thread in 2013.

On Mar 9,

Jim Thompson could probably remember a better solution for you. The long-obsolete MC10198 ECL monostable

Something boringly obvious with a constant current ramp and a fast comparator would do the job, but - as with the MC10198, being able to switch in bigger capacitors to generate much longer pulses is probably incompatible with a 10nsec pulse width.

The only parameters that I see in the ECLTN0E model that differs from it's 'grouping', is a half order magnitude reduction in all junction capacitances - this feature acting to prevent oscillatory behavior, monostable or otherwise. It's ECL companion models oscillate (astable) generally, despite Rbb parameters ranging over two orders of magnitude, in this circuit configuration.

RL

The broad-band transistors - of which the BFR92 is the most obvious example - famously have low collector base feedback capacitance, and a very thin base layer (2V base to emitter breakdown voltage).

Looking at the parameters, without thinking about the transistor behaviour that that they are intended to model, isn't a constructive or useful activity.

When I was working for Cambridge Instruments were selling the EBMF10.5 electron beam microfabricator to write the fine-line masks that made those sorts of devices.

Sometimes they were used to direct-write very fine features on particularly exotic (and expensive) devices. On one occasion the acceptance test for the machine was to write three wafers full of devices, which - when diced and package - would have paid for the million-odd dollar price of the machine.